Why? In small sequential access case, it's should be close to full bandwidth (larger sequential access case will have problems with timing, since other memory controllers will have to wait for the one with bigger memory). In random access case, the memory controller with big memory does not have to always do two bursts since it's quite possible that one burst can cover the data you want and you don't have to do both bursts.
Of course, we don't know for sure how NVIDIA does it without further testing. It's possible that NVIDIA did it the simple way and put all extra memory in a single memory controller. Since the CUDA bandwidth test doesn't seem to tell much (although, if the test does very large sequential access, it could hit timing problem if the memory is interleved as said in my post), I think we'll have to wait for more data to find out.
[EDIT] I think there are two cases here: the first one is that CUDA only exposes ~768MB memory, which suggests that NVIDIA uses a "flex" model (all extra memory in a single controller), and NVIDIA does not want to expose the slower memory region to GPGPU applications. However, another one is the CUDA bandwidth test, which seems to suggest that the effective bandwidth is the same as a 450 (clock normalized). This seems to suggest a full interleave model.
I think memory management for a "flex" model is probably not very hard. NVIDIA may simply make the extra memory as some kind of "faster Turbo cache." They already have management code for TC so it's easier to reuse them. The downside of a full interleave model is that when you are actually doing a lot of sequential memory access you'll have to wait for the slowest one (i.e. the memory controller with the bigger memory) and it will bring down performance to roughly equivalent to a 128 bits bus. Although in general 3D rendering does not do a lot of large sequential access, sometimes it still needs to do them especially in deferred shaders.
