Is it over 9000????! Yes.. barely.
Well yes the chips should be able to do higher, obviously. However, I'm not sure if that'll be very practical. As long you only increase clocks it should be fine but probably not that much headroom. If you increase voltage and clocks to GTX 580 levels, you're looking at 600W (unthrottled) furmark power consumption, and even in games you will reach about 500W. I don't know if the card is built to really handle that (VRM) or just goes up in smoke, but even if it is you'll almost certainly need ear protection (not that this would be different to the OC HD 6990). Sure if all you care is "highest 3dmark score" then that doesn't matter, but otherwise you probably need some more investments in water cooling.by this "nVidias "AUSUM equivalent"" I'm not saying that it'll have a switch or anything, but just regular OC by the end user, but who knows maybe it'll have a switch...Also I'm not saying that the OC headroom will be awesome, if the stock voltages are low, but once the voltages are cranked up to regular GTX 5xx levels, it should fly.
Well yes the chips should be able to do higher, obviously. However, I'm not sure if that'll be very practical. As long you only increase clocks it should be fine but probably not that much headroom. If you increase voltage and clocks to GTX 580 levels, you're looking at 600W (unthrottled) furmark power consumption, and even in games you will reach about 500W. I don't know if the card is built to really handle that (VRM) or just goes up in smoke, but even if it is you'll almost certainly need ear protection (not that this would be different to the OC HD 6990). Sure if all you care is "highest 3dmark score" then that doesn't matter, but otherwise you probably need some more investments in water cooling.
maybe they tested the 768 MB model?any comments why GTX 460 numbers half of actual numbers??
http://www.bit-tech.net/news/hardware/2011/03/15/kfa2-plan-gtx-560ti-sli-on-a-single-pcb/1KFA2 plans dual GTX 560 Ti graphics card
The keen eyed among you may notice that the prototype board pictured below sports a pair of GF104 GPUs, similar to those found on GeForce GTX 460 cards. However, KFA2 claims that this is because it originally developed the card for the GF104 chip. The company says it's since decided to upgrade the card's GPUs to the GF114 chip found on new GeForce GTX 560 Ti cards.
maybe they tested the 768 MB model?
edit: or are these your own numbers? In that case it might be simply a bug, maybe even the same bug as with the 550 Ti (mentioned in the 550 review on anandtech).
Why would that happen ? the way I understand it , is that there are two 64-bit controllers with 1Gb chips , and one 64-bit controller with 2Gb chips , the reduced bandwidth could only occur in the last controller , why would it happen across the entire array ?GF116 has 3 64-bit memory controllers, each of which is attached to a pair of GDDR5 chips running in 32bit mode ... The best case scenario is always going to be that the entire 192-bit bus is in use, giving the card 98.5GB/sec of memory bandwidth (192bit * 4104MHz / 8), meanwhile the worst case scenario is that only 1 64-bit memory controller is in use, reducing memory bandwidth to a much more modest 32.8GB/sec.
Anand's GTX 550 review :
Why would that happen ? the way I understand it , is that there are two 64-bit controllers with 1Gb chips , and one 64-bit controller with 2Gb chips , the reduced bandwidth could only occur in the last controller , why would it happen across the entire array ?
That may be but what happens once you have equal amounts in all 3 pools, but there's still excess capacity in the 3rd pool with the 2Gb chips?
So is it just that anything above 768 MB limited to 32.8 GB/sec?
Regards,
SB
Generally it's not assigned this way. It's more likely to be interleaved. For example, you can assign byte 0 ~ 15 to the first memory chip, 16 ~ 31 to the second, 32 ~ 47 to the third, and 48 ~ 63 to the fourth, etc.
In the case of one memory controller has a larger memory chip, you'll have to assign two interleaved sections to that controller, such as, 0 ~ 15 for the first, 16 ~ 31 for the second, and 32 ~ 63 for the third (and there's no fourth memory controller).
If your access pattern is linear (sequential) or truely randomized, it should be very unlikely that all your memory access hit the third memory controller.
If you do it that way for all the memory, you'd effectively have a 128bit controller however (half the data in the 3rd controller).In the case of one memory controller has a larger memory chip, you'll have to assign two interleaved sections to that controller, such as, 0 ~ 15 for the first, 16 ~ 31 for the second, and 32 ~ 63 for the third (and there's no fourth memory controller).