NVidia Ada Speculation, Rumours and Discussion

I didnt talk about gaming rendering. I specificed mention compute performance. A chiplet design will scale worse than a monolith chip card in games.... But people here expect that AMD will increase compute performance by 2.5x over RDNA2.

nVidia did it with Ampere and specific compute performance without increasing other units like rasterizer, geometry units etc:

https://techgage.com/article/mid-2021-gpu-rendering-performance/

You can only invest so much transistors.

 

Let say GPUs tend to be designed with the idea that more (well, many more) than 1 warp is running on a processor at any given time

 

RDNA needs 4 distinct "warps" each cycle to fully load its WGP. Unlikely to be any sort of real issue going from real world results.

 

An RDNA WGP needs 4 distinct warps with lots of ILP. If there's no ILP it needs a lot more warps (5 cycle dependent math latency IIRC).

Turing was the same, needed 4 distinct warps with lots of ILP for maximum FMA throughput. Not sure if that changed for Ampere. However, it doesn't say anything about the extra INT/FP32 pipe. Presumably you need 4 additional warps with lots of ILP to keep that second pipeline going.

Have we seen better?

 

If bandwidth played an important role, RTX 3070 should stand out more, since it's got a notable uptick in GFlops/GBps and should do worse, which it doesn't.

Maybe it's got something to do with what this test does - compared to other tests in Luxmark 4 alpha:
"The second LuxMark benchmark is a path tracer with global illumination cache. This rendering mode slightly simpler than pure brute force and may work better on some GPU."
https://wiki.luxcorerender.org/LuxMark_v4
Especially the GI cache sound like RDNA2 might profit. Maybe we'll see numbers with RX 6600 XT showing a trend here.

Fun fact: most efficient GeForce is the 2080 Ti, when you compare points per GFlops.


Maybe power budget plays a role? I seem to remember, RTX 30 cards were boosting theirs hearts out on Luxmark, running quite a bit higher than their advertised boosts; at around 1900 MHz, IIRC.

Maybe also a larger cache would help. Something Lovelace will fix?

 

Yeah it's reasonable to assume that issuing to the tensors would preclude issuing to one of the other SIMD pipes in the same cycle. I'm not sure that's important though as we don't double count tensors when talking about peak Ampere flops available to graphics applications. We know that FP16 throughput is 2xFP32 and the assumption is that one data path is sufficient to provide the necessary operands. So whether FP16 is running on the main SIMDs like RDNA or on tensors like Turing/Ampere doesn't really matter.

Nvidia has usually been explicit about the number of instructions dispatched per cycle and in Ampere it's one instruction per partition. So presumably Ampere can only issue to one execution unit each cycle including the load/store units.

I don't quite get your comment about 4-way issue though. Graphics applications don't need to issue to the tensors to achieve "peak utilization" in the way it's currently defined which is 128 FMAs per clock. When we're talking about scaling of graphics or compute applications that's the number we're referring to.

 

FWIW, Ampere as well as Turing uses the Tensor Cores for standard FP16 math.

 

Yep, the Ampere issue options are:

16xFP32 + 16xFP32
16xFP32 + 16xINT32
16xFP32 + 32xFP16 (tensor) ---> need to confirm if tensors can co-issue with one of the SIMDs

 

Who's said that async was worse in RDNA?
It's obviously not, but AMD did nothing to improve async compute in RDNA and they did refactor graphics pipeline to minimize stalls and improve latencies with the new 32-wide wavefronts, that was the whole reason behind better RDNA efficiency.
When you compare Radeon VII to 5700 XT, NAVI10 achieves way higher efficiency at the same average performance mostly because instead of filling in the pipeline bubbles with async compute (impossible to fix automatically in HW) they decreased the number of the pipeline stalls in the first place.

Because there is 0 demand for the 7 times higher resolution displays (most of PC displays are still 1080p, 1440p is second most popular resolution and 4K still captures a minor fraction of PC market), geometry processing takes pretty much constant time in all resolutions, etc, etc.
If you look carefully, you would probably notice that most of games don't scale linearly with resolutions for tons of reasons (not just CPU), only the heaviest (thanks to RT and compute) games like CP2077 do scale linearly with pixels, but that's exactly type of games where RTX 3090 is up to 2x faster in comparison with RX 6900 XT currently.

 

Volta can dispatch instructions for 2+ data paths.
I guess the + means that SFU instructions running for 8 clocks can be overlapped with INT and FP instructions.

 

I'd say most dont have anything against amd and in special NV increasing GPU capabilities. About three times the power of the consoles in just normal rendering aint a bad start, thats aside from ray tracing and reconstruction counted in. The enormous compute power enables things like UE5/lumen/nanite aswell.

 

FP16 is same speed as FP32 on Ampere. Which likely means that you can't do the + there.

 

It doesn’t though since nobody counts tensors when talking about theoretical flops for gaming.

Maybe. But the topic was how application performance scaled with Ampere’s doubled FP32. We have lots of evidence that game performance did not scale anywhere close to the flops increase. However there are other workloads where it came reasonably close.

Ok.

 

You achieve peak FP16 flops on Ampere by issuing a wave-32 of packed FP16 FMA operands (64 sets total) to the tensor pipe. Presumably the tensors will take 2 cycles to process the wave. What’s preventing the SM from issuing a wave-32 of FP32 instructions to one of the other SIMDs in the next cycle while the tensors are still chewing on the FP16 data?

Or do you mean that tensors process the full wave in one cycle so there’s no opportunity to run tensors in parallel with other work?