NV30 not taped out yet....

[RussSchultz]

Sigh. Fab times are fairly set in stone, and any analyst of the semi market would know these.

6-8 weeks for first silicon +
1 month for verification +
2-3 months in the fab for production =
too late for Christmas. (not even considering any metal revs)

What I'm suggesting is there is no way for him to pull the wool over any analysts eyes, so why would he try?

 

[nooneyouknow]

They can take a gamble, albeit huge, and start production in parallel with verification. Thus, they could hit the holiday season IF everything is perfect (or at least work-around-able via drivers.

 

[kid_crisis]

From the CC on July 11th, Jen Hsun clearly stated that the NV30 would be on a 0.13um process with copper interconnects, and that low-k dielectrics were NOT to be used (no doubt because TSMC was having problems with them).

By the way, someone stated previously that low-k dielectrics were only useful on chips of 1-GHz frequency or higher. This is not fully correct since the low-k dielectric (where k = relative dielectric constant to air) will reduce the capacitance of any metal line placed on it. The speed of a chip is usually limited by the RC (resistance-capacitance) time constant that limits charge propagation speed along the interconnect lines. You can reduce this time delay (which increases clock speed) by reducing this RC product, i.e. by either reducing the resistance or the capacitance (or both)of the interconnect line. The copper interconnects reduce the resistance versus what is normally used for metal interconnects in the silicon world, either aluminum or gold (copper is the best "normal" electrical conductor, where by normal I mean not a super-conductor). Copper interconnects are considered an advanced process because copper tarnishes more easily than gold or aluminum, but the payoff is faster circuit operation.

To give a mechanical equivalent for visualization, the metal interconnect can likened to a garden hose, and the water squirting through it is the electrical current. The electrical-resistance of the line is the diameter of the hose, the lower the resistance the bigger the diameter. The capacitance of the line can be likened to holes or leaks in the line. Lowering the lines capacitance is like plugging up a percentage of these leaks. Either increasing the hoses diameter OR plugging some of the leaks will increase the amount of water going through the line. The higher the flow rate of water, the faster the transistor it is driving will switch state, since it takes a certain amount of water (electrical charge) to turn the transistor on or off.

So I guess my point is that the copper interconnects will increase speed somewhat, but if they were to also to use a low-k dielectric underneath the lines, it would increase the clock speed even more (assuming the timing of the chip allowed for it of course).

 

[KimB]

I doubt the low-k dielectrics would make much difference for lower clock speeds, as the capacitance, more or less, sets a maximum possible clock speed (in addition to other factors...). There won't be much effect of capacitance until you start to get reasonably close to that clock speed.

And a little point: the "k" number is in respect to a vacuum. Air has a very small, but larger than 1, dielectric constant.

Personally, I don't really see how capacitance can be likened to "leaks." Capacitance is basically a limitation on how quickly a current can change. So, if you're using the analogy of the hose again, capacitance may be likened to rust in the valves, slowing how quickly you can change the amount of water going through the hose (But, not a very good analogy...as capacitance has little to no effect when the changes in current are relatively slow).

But, I will have to say that I don't really know at about what clock speed the low-k dielectrics would make a difference, as that would depend upon how the chips are manufactured (in particular, how far apart the various circuits within the chip are...and even then, I'd only be able to give a very rough estimate, as it's a very complex system). I wouldn't be surprised if the 1GHz number was correct, though.

 

[demalion]

What's this Tom's Hardware article worth? Ignoring the "ridicule someone else to sound cool" tone that seems Omid's favored writing style nowadays, some of the info seems to solidify some suppositions about the issues. We can atleast wait and see if nVidia asks for any retractions or makes some comments, and can maybe learn from whether they do that or not.

 

[T2k]

What's this Tom's Hardware article worth? Ignoring the "ridicule someone else to sound cool" tone that seems Omid's favored writing style nowadays, some of the info seems to solidify some suppositions about the issues. We can atleast wait and see if nVidia asks for any retractions or makes some comments, and can maybe learn from whether they do that or not.

The article is ridiculous, sure. But only 15% yield??? Sounds really weird for me...

 

[Nagorak]

Sigh. Fab times are fairly set in stone, and any analyst of the semi market would know these.

6-8 weeks for first silicon +
1 month for verification +
2-3 months in the fab for production =
too late for Christmas. (not even considering any metal revs)

What I'm suggesting is there is no way for him to pull the wool over any analysts eyes, so why would he try?

Nothing is set in stone. I mean, there's a "chance" that the subatomic particles floating through space will come together in just the right way to cause a completed NV30 to coallesce out of thin air. Granted it's so unlikely it wouldn't happen even in a Quadrillion years, but there's always the chance.

So he could just be being overly optimistic, like I said.

 

[Guest]

Because dates, etc don't add up. If it hasn't done its initial tapeout, then it will not get back even close to in time for products to be on the shelf for the holiday season. But the CEO suggested it should. Very curious.

As I said, the magic 8 ball says "Cannot Predict Now" and "ask again later". I'm sure tomorrows story will be different.

Maybe because he's the CEO!!!! He wants to make as optimistic projections as possible, whether or not they have more than a slim chance of coming true.

I agree Nagorak, the CEO of nvidia is not nessesarily the person we should be listening to..... and it is his job to put up the "window dressing". Further the guy according to rumors had already claimed that the NV30 was already taped out at last CC but now would catagorically deny it, how can we believe anything the man has to say now? I am surprised that even after the CEO has stated that the NV30 is NOT taped out that their is even any question about it... Still there are a few whom would pretend to not know. My best estimate is that the nv30 will not be on any store shelves till after the new year by January at the eariliest. Unless of course Nvidia can pull a rabit out of the hat so to speak.

 

[Gollum]

You're welcome.... Honestly, I had never heard of "Chang", but since he used it I assumed "Chang" was simply someone at nVidia of whom I was unaware. Well, that's what I get for a-s-s-uming, right?....

Whoops ... cough ... jup I screwed up the name, sorry for that.

 

[Tahir2]

I think, even though I am not sure, Jensun Chang would be the phonetic variant of Jen-Hsun Huang and that may be where the confusion arose from.

 

[WaltC]

Technically NVIDIA already released a product for the second half of 2002 (the N-Force 2) so I don't see how they could really miss out on their 6 month product schedule. Still, it would be rather disappointing to have to use that as the only example of keeping their word.

When nVidia started their "6-month cycle" publicity stunt, however, they were strictly speaking about GPUs as at the time they weren't making anything else.

But really...it was a strange thing to declare in the first place. It did have some PR value in terms of shaking out the companies who could not execute as fast at the time (like 3dfx), and lighting a fire under ATI, but holding one's self to an arbitrary 6-month product cycle just seems ludicrous, to me. It should be ready "when it's ready"...and such goals should be targets not declarations. It's just been a matter of time until nVidia reached the point of diminishing returns with respect to this policy. As GPUs grow fantastically complex their rate of evolution has to slow somewhat else we'll get an avalanche of unfinished silicon floating around the market...

 

[WaltC]

Whoops ... cough ... jup I screwed up the name, sorry for that. [/quote]

No biggie for me. I can see how hearing "chang" verbally might cause you to write "chang" instead of "Huang".... It didn't occur to me, either, so you're in good company.... 8)

 

[Guest]

Technically NVIDIA already released a product for the second half of 2002 (the N-Force 2) so I don't see how they could really miss out on their 6 month product schedule. Still, it would be rather disappointing to have to use that as the only example of keeping their word.

When nVidia started their "6-month cycle" publicity stunt, however, they were strictly speaking about GPUs as at the time they weren't making anything else.

But really...it was a strange thing to declare in the first place. It did have some PR value in terms of shaking out the companies who could not execute as fast at the time (like 3dfx), and lighting a fire under ATI, but holding one's self to an arbitrary 6-month product cycle just seems ludicrous, to me. It should be ready "when it's ready"...and such goals should be targets not declarations. It's just been a matter of time until nVidia reached the point of diminishing returns with respect to this policy. As GPUs grow fantastically complex their rate of evolution has to slow somewhat else we'll get an avalanche of unfinished silicon floating around the market...

I think the drive for the 6 month product schedule came from a wanting to be perceived as an "Intel like" company. Nvidia touted this message often in the past and I believe it had more to do with the investment community and the companies stock price then actually making viable upgrades every six months. Other targets like nforce and the xbox have weighed them down to an extent.. But in this matter Nvidia really has been caught off guard by ATI and the Radeon 9700s power. This is forcing them to go beyond their regularly scheduled program.

The NV30 has been put to the forefront of nvidias objectives(IMHO) because the Radeon 9700 soundly beats whatever they had intended for the market to compete with ATIs next gen part. Otherwise nvidia would have been all over the Radeon 9700 launch like a wet blanket, to douse ATIs Radeon 9700 launch.

 

[KimB]

The six-month cycle was set in order to synchronize with OEM product cycles.

 

[Guest]

The six-month cycle was set in order to synchronize with OEM product cycles.

I doubt it... Why are OEMs still mostly carrying geforce2 MXs?

 

[KimB]

Not just computer manufacturers...board manufacturers too, I believe. Anyway, I remember specificially an nVidia employee stating the reason for the six-month product cycle. nVidia always wanted to have a shiny new chip whenever anybody who wanted to sell products with video chips in them was ready to ship a shiny new product.

 

[Nagorak]

Nvidia never really had a 6 month cycle if you consider "new" architecture.

I mean it was GF1, then GF2 which was basically the same design. Then the GF3 took so long that they had the GF2: Ultra . In fact the GF2: Ultra was barely any less of a step forward than GF1-GF2 (although there were some minor changes between 1 and 2), so it seems to me they could have just called it GF3 for the PR value.

Anyway, then we had GF3 and GF3:Ti which are basically the same card, and finally GF4 which is just a revised GF3.

In other words if you look at the pattern, each next gen architecture is actually taking them 1.5 years. The 6 month cycles are just refresh parts. Meanwhile ATi has been putting out entirely new architecture every year with a refresh at the same time (Radeon becomes R7500, R8500 becomes R9000).

So actually if you think about it, ATi has been producing entirely new products at a faster rate. When you look at it that way, it's not really surprising that the R300 beat the NV30 to market. Although the NV30 has been delayed or it'd be out at the same time. I really think Nvidia needs to re-evaluate their strategy because they've gone from having a 1 year lead (GF1, GF2) to a 6 month lead (GF3) to no lead (NV30, although they're actually behind now due to their delays). If the "6 month cycle" is adding 6 months to their new architecture cycles, they just can't afford to keep it up.

 

[KimB]

Actually, nVidia was on a one-year new architecture cycle until the GeForce architecture was in for 18 months.

I do wonder whether or not they will switch back to a 12-month new architecture cycle, given the increased competition by ATI.

 

[Entropy]

Actually, nVidia was on a one-year new architecture cycle until the GeForce architecture was in for 18 months.

I do wonder whether or not they will switch back to a 12-month new architecture cycle, given the increased competition by ATI.

As far as I can remember, the TNT was on .35, GF256 was on 0.25, GF3 was on 0.18 and NV30 will be 0.13um. Regardless of shaky memory, that pattern makes sense because given a set of constraints, what brings the possibility of new solutions is new process technology. If the process didn't change, it would be very strange if a company kept coming up with new architectures given the same transistor/power/size/cost budget. Assuming that nVidia is on the ball, it would be reasonable for them to introduce a new architecture at every major new step downwards in lithography.

That would still be very aggressive compared to CPUs. The Athlon was introduced at 0.25 and has only seen very small revisions down to 0.13 via 0.18 and may or may not be with us down to 0.09. The Pentium Pro => Tualatin was even longer, and the P4 is projected to be around for at least four steps downward in geometry.

GPUs are still at a stage where they add more functionality as transistor budgets increase, and they can always increase parallellism. I'd guess that transistor counts will probably continue to grow at a faster rate than CPUs, unless we start seeing multi-cored CPUs.

Entropy

 

[Bigus Dickus]

On capacitance and the hose analogy:

If my system dynamics course has stuck with me, then capacitance is, technically speaking, analogous to a resevoir in a fluid system.

In this hose analogy, capacitance would be a sort of "bulb" or "tank" in the middle of the hose, which must be filled before the fluid can continue on to the other end. Reducing the size of this "tank" reduces the time needed to fill it, and speeds delivery of fluid to the destination (transistor).

The odd thing is that the volume of the hose itself is a sort of resevoir, that has to be filled completely before fluid makes it out the other end. By enlarging the hose you can decrease resistance, but increase this "line capacitance." I'm not sure if this analogy works the same way in electrical systems, but since the mathematical relationships are identical, my guess is that it does. So, the goal then is to decrease interconnect resistance by changing material, not widening the interconnect (which goes against miniaturization anyway).

Now, Low-K dialectrics are doing something a bit different though, and I think you could correctly think of them as "plugging the leaks" in the hose. Essentially, the surrounding material also has to be "filled" in a certain sense (think of this as saturation) like a resevoir. Using the hose analogy, think of the hose lining to be somewhat porous. If the surrounding material has a high capacitance (large resevoir, or storage capacity), like a sponge, then it will take a long time to saturate that sponge and start propagating water through the hose instead of into the sponge. If the surrounding material has a low capacitance (low storage capacity), like concrete, then very little fluid needs to leave the hose, and it reaches the other end much more quicly.

Bah, I'm a mechanical guy, not an electrical guy, so this could be off. The systems are mostly interchangeable though, and the analogies aren't mearly for making things easier to think about... you can exacly duplicate an electric circuit with a fluid or mechanical system equivalent. The equations are the same for all three (with minor caveats).

For a refresh (and I'm doing this from memory, so don't laugh too hard if I screw it up )

Mechanical:		Fluid:			Electrical:

Mass			Resevoir		Capacitor/Capacitance
Damper			Resistance		Resistor/Resistance
Spring			Inertance		Inductor/Inductance
Velocity		Flow rate		Current
Force			Pressure		Voltage