LeStoffer said:Maybe, just maybe, the NV30 isn't really delayed according to nVidia's own internal timetable.
Initialy, NV30 was target to be the spring 02 product. Then there was the GF3 delay and as a consequence of this the GF4 delayed as well. The NV30 became the fall part. Now we seem to have another delay ...
I don't believe, however, that there was any delay due to "hey, we need to add a 256 bit bus also!". The major design cannot be changed, but some minor tweaking after the test simulation might have taken place during the last month or so.
Yes, I agree. The bus size and therefore the memory bandwith expected is a key design target, you build your architecture around this, designing cache sizes, number of TMUs, pipelines, memory controller and decide how much engineering effort has to be put into bandwith saving features (or not). Simply adding more memory bus lines late in the process brakes down your architecture design.