Sorry guys, but i can't post links. I recommend search for Gen-Z it might be the key for PS5 and the integration of IF2, HBCC and SSG.
The Gen-Z switch: The backbone of Gen-Z fabric
April 9, 2019
By Tim Symons, Storage Architect, Microchip
Gen-Z fabric incorporates a number of features for enabling low-latency, memory-semantic communication, and one of the key components of the Gen-Z ecosystem is the Gen-Z switch. The Consortium showcased a Gen-Z switch at Flash Memory Summit 2018 as part of our multi-vendor technology demonstration. The server rack display utilized Field-Programmable Gate Array (FPGA)-based Gen-Z bridges connecting compute nodes to memory pools through a Gen-Z switch.
The Gen-Z switch is backbone of the Gen-Z fabric. It is essentially a component or component-integrated functionality that performs packet relay between component interfaces. The configuration of Gen-Z fabric is achieved and managed by a Fabric Manager that identifies all of the components attached to the fabric and executes policies for managing packets, creating domains, sub-domains, and access privileges by configuring the switches within the fabric. Fabric management is in-band using Gen-Z commands over Gen-Z connections.
To enable its full functionality, Gen-Z memory fabric involves switching, routing, security, zoning, access control and fabric management. The core properties of Gen-Z fabric consist of:
- Scalable and provisioned memory infrastructure
- Shared memory for data processing
- Connectivity of processors, GPUs, accelerators, and optimized engines
- Next generation DRAM, FLASH and storage class memory
- Enabling persistent memory
These characteristics are configurable to meet application needs by managing access to memory domains, high-speed routing zones, and processing domains. Fabric switches can interconnect to create a larger infrastructure and can also be provisioned into multiple subdomains and zones designed to support variable application workloads and system requirements.
Local switches enable small-scale Gen-Z fabrics, as well as routing and provisioning of resources with minimal switching latency and almost transparent routing. Peer-to-peer operation codes within the fabric ensure that direct attached memory is among the lowest latency Gen-Z fabric configurations.
Finally, it’s important to note that data integrity is paramount. Cyclic Redundancy Check (CRC) is performed at three levels: on the packet header, within a packet and optionally for each PHIT, to ensure error detection and to eliminate the possibility of a false packet acceptance.
At the higher link rates (53.125 Gb/s and above) Forward Error Correction (FEC) is implemented to correct PHIT bit errors that ensures data integrity and minimize retry events to optimize bandwidth utilization.
Gen-Z is truly the fabric for next-generation workloads. As the amount of data and multi-processing demands continue to increase, a high-bandwidth, low-latency interconnect is now imperative to meet the industry’s needs. Gen-Z technology delivers business and technology leaders a solution for overcoming current challenges within existing computer architecture and presents open, efficient, simple and cost-effective future solution opportunities.
The
Gen-Z consortium is a trade group of technology vendors involved in designing
CPUs,
random access memory, servers, storage, and accelerators. The goal was an open and royalty-free "memory-semantic" protocol, which is not limited by the memory controller of a CPU. The basic operations consist of simple loads and stores with the addition of modular extensions. It is intended to be used in a switched fabric or point-to-point where each device connects using a standard connector.
[1]
The consortium was publicly announced on October 11, 2016.
[2] Server vendor members include
Cisco Systems,
Cray,
Dell Technologies,
Hewlett Packard Enterprise,
Huawei,
IBM, and
Lenovo. CPU vendor members include
Advanced Micro Devices,
ARM Holdings,
Broadcom Limited, IBM, and
Marvell (formerly
Cavium). Memory and storage vendor members include
Micron Technology,
Samsung,
Seagate Technology,
SK Hynix, and
Western Digital. Other members include
IDT Corporation,
Mellanox Technologies,
Microsemi,
Red Hat, and
Xilinx.
[1] Analysts noted the absence of
Intel (which announced an inter-connect technology of its own called
Omni-Path a year before) and Nvidia (with its own
NVLink technology).
[3] Some of the vendors also joined a group to promote the
Cache coherent interconnect for accelerators (CCIX) protocol on the same day.
[4] At about the same time, yet another consortium formed to work on an open specification for the
Coherent Accelerator Processor Interface (CAPI).
[5] The efforts followed years of delays before products were available with version 4.0 of
PCI Express.
[6]
Last one.
Customers are demanding new levels of performance, functionality, security to solve the growing challenges associated with processing and analyzing massive amounts of data in real time, while avoiding today’s system bottlenecks and security risks. After many months of investigation, the member companies determined that a new, comprehensive data-access technology was required – one that could support a wide range of new storage-class memory media, new hybrid and data-centric computing technologies, new memory-centric solution architectures, and a wide range of applications using a highly-efficient and performance-optimized solution stack.
Gen-Z is the solution. It is an open-systems interconnect designed to provide memory semantic access to data and devices via direct-attached, switched or fabric topologies. This means Gen-Z will allow any device to communicate with any other device as if it were communicating with its own local memory using simple commands. Sometimes called load/store protocol, we refer to it as a “memory-semantic communications” because it uses the same language as local memory does today. Memory-semantic communications are used to move data between buffers located on different components with minimal overhead. For example, Gen-Z-attached memory can be mapped into a processor memory management unit (MMU). Any processor load, store, or atomic operation is transparently translated into Gen-Z read, write, or atomic operation and transported to the destination memory component. Similarly, Gen-Z supports buffer "put" and "get" operations to move up to 232 bytes of data between buffers without any processor involvement.
This leads to much simpler software and hardware, and this simplicity drives performance and lower costs. Gen-Z will provide this memory-semantic connectivity to devices including System on a Chip (SoC), data accelerators, storage, and memory on the motherboard and beyond the motherboard to rack scale. In practice, that means that Gen-Z will deliver businesses more flexibility, performance, efficiency, and choice in the design and configuration of their core data center technology investments, all connected in a unifying industry standard interconnect.
