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Next Generation Hardware Speculation with a Technical Spin [pre E3 2019]
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Handy! Good work @anexanhume.Maybe this can help. It's from anexanhume!
I think a 256-bit bus is a very border line solution with GDDR6. I don't think the 18/20 Gbps chips will be a good fit for the console space. And if it's a shared pool of memory, 512GB/sec may not be enough to split between a much more powerful CPU and GPU. I think they need to go with a bigger bus, but maybe it doesn't have to be a fully enabled bus (320-352 bit ?).
I was thinking about the comment I made earlier that the two stacks of HBM may be insufficient as they would only provide 410 GB/sec. However on more thought, I hope Navi is a lot more efficient then Polaris/Vega and closer to what Nvidia can achieve with Turing. RTX 2080 only needs 448 GB/sec. If AMD can improve the memory utilization and efficiency of their microarchitecture that will go a long way to alleviating the need for a very high bandwidth solution.
I was thinking about the comment I made earlier that the two stacks of HBM may be insufficient as they would only provide 410 GB/sec. However on more thought, I hope Navi is a lot more efficient then Polaris/Vega and closer to what Nvidia can achieve with Turing. RTX 2080 only needs 448 GB/sec. If AMD can improve the memory utilization and efficiency of their microarchitecture that will go a long way to alleviating the need for a very high bandwidth solution.
https://www.resetera.com/threads/xb...everyone-plays-we-all-win.94058/post-20204348
So Klobrille is admitting that Lockhart and Anaconda will use a Navi GPU?
So Klobrille is admitting that Lockhart and Anaconda will use a Navi GPU?
What else would they be using as a base architecture? That's what AMD will have available during the assumed release time frame. Note that being based on the Navi architecture doesn't mean that the SoCs will just be straight copies of the PC parts AMD is developing. There will almost certainly be some degree of customization.
I speculated a couple of days ago that a 1TB QLC drive would be sufficient to use as a cache from a hdd or external sources. It's big enough to keep ten or more of your most played games resident and could conservatively handling 2000 copies-in of even a huge game like RDR2 (probably more like 4,000+ in reality). Nvme would also make the drive replaceable (edit: maybe not - hopefully MS would take a leaf out of Sony's book and make it user replaceable.
16GB of ram would be loads if you had a 7GB/s nvme drive. Even 12 would be fine.
1TB HDD in the base model, 2TB in the top, and replace with a single SSD when cheap enough.
16GB of ram would be loads if you had a 7GB/s nvme drive. Even 12 would be fine.
1TB HDD in the base model, 2TB in the top, and replace with a single SSD when cheap enough.
I was expecting navi so much that it didn't even register that that was a confirmation (as much as believing this)
But about a week ago I laid out how I felt it was possible to be post navi based on original timelines. Navi delayed, post navi still on schedule and fact that both probably being developed in parallel.
To be clear not what I expected
Sony's fiscal year is funky, off by a quarter compared to calender year.
I can only assume the remaining options are vega and other?
anything is possible with MS, I don't think it was blatantly assured of which direction they were going with next gen and how much cross over this server stuff might have on the console. Granted, the best probability was to go with Navi especially after seeing Sony declare Navi.
but when Google went Vega, and recently finding out that Navi is just the progression of Polaris - perhaps having more compute focused chip would net more benefit for MS when it comes to leverage compute on the web for idle time on those streaming SOCs for instance.
I wasn't entirely sure which way things could have gone.
Navi would be an evolution of what customization they have been working on with Polaris and X1X; so perhaps it makes more sense to continue from this platform instead of chasing profits for selling online compute.
Also better they have the same architecture as Sony to be an open door for them if Sony want to move PS Now over to Azure.
I would've liked it to be different than navi, just for discussion.
I'm still hoping storage, memory, and customisations will be different enough.
I prefer talking about this stuff than finding time to play games
Well, yeah. You build a gaming-focused part for your gaming-focused products. I'm not sure I'd characterize Navi as not being a continuation of Vega, though. I expect some elements of that architecture will be brought forward into Navi (HBCC, RPM, etc.).
Both companies are potentially rolling a Frankenstein given the modular nature of the gfxip blocks. Things that appeared with Tonga or Polaris or Vega clearly aren't limited to those codenames; the midgen twins kept a lot of things from Sea Islands for compatibility while bolting on other bits that RTG either already had or was developing which happened to appear at various stages in their usual markets.
? And what does that mean for possible transistor counts and clocks?
<ocd>
Silly question triggered off OCD thoughts. Does the nomenclature of "7nm +" bug anyone else? What I mean is the writing converys "7nm or better" meanwhile the plus (+) on a number conveys larger, like 7+ would be 8 or 9 or larger than 7, and we know bigger nm is not better. So should this really become "7nm -" ?
</ocd>
Silly question triggered off OCD thoughts. Does the nomenclature of "7nm +" bug anyone else? What I mean is the writing converys "7nm or better" meanwhile the plus (+) on a number conveys larger, like 7+ would be 8 or 9 or larger than 7, and we know bigger nm is not better. So should this really become "7nm -" ?
</ocd>
Isn't 7nm + just 7nm EUV ?
I'm new here not as tech savy, i've read every single post in this thread from the day Mark Cerny talked about the next-gen console.
My guess is that the key to understand the "PS5" design is knowing how infinity fabric(2nd gen), HBCC and SSG technologies can work togheter on a single PCB.
Consoles as closed systems don't need to follow the same strict protocols as PCs, but Cerny certainly knows that diverging too much, without giving an automatic mode, to compensate the differences can cause some "backslash" to 3rd party devs, PS3 was a life lesson to not be repeated.
PS4 back compat requirements are somewhat restrictive when projecting the newer system, with latest Cerny's patents we can almost guarantee that it will use "hardware emulation" for 100% compatibility.
Guesstimation
I believe that it will have at least ~128GB (slightly bigger than an UHDBD disk capacity) "SSD like" memory soldered on the PCB (physically close without handshakes, new protocol) with direct access lanes to all components that needs to be fed from it, plus a "sata 4.0?" connection for a probably less expensive and more reasonable secondary storage solution, (2TB?) and compatibility with all major storage solutions.
My guess is that the key to understand the "PS5" design is knowing how infinity fabric(2nd gen), HBCC and SSG technologies can work togheter on a single PCB.
Consoles as closed systems don't need to follow the same strict protocols as PCs, but Cerny certainly knows that diverging too much, without giving an automatic mode, to compensate the differences can cause some "backslash" to 3rd party devs, PS3 was a life lesson to not be repeated.
PS4 back compat requirements are somewhat restrictive when projecting the newer system, with latest Cerny's patents we can almost guarantee that it will use "hardware emulation" for 100% compatibility.
Guesstimation
I believe that it will have at least ~128GB (slightly bigger than an UHDBD disk capacity) "SSD like" memory soldered on the PCB (physically close without handshakes, new protocol) with direct access lanes to all components that needs to be fed from it, plus a "sata 4.0?" connection for a probably less expensive and more reasonable secondary storage solution, (2TB?) and compatibility with all major storage solutions.
Certainly a big piece of the puzzle; data transfer between different systems seems to be the most important topic that may not necessarily introduce additional costs like devoting more silicon to compute would
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