Next Generation Hardware Speculation with a Technical Spin [pre E3 2019]

[Deleted member 13524]

I'm saying this news isn't very useful to us. Having a code that deciphers to 'unknown' isn't all that informative.

Chris1515 posts exciting code. What does it mean?? A cheetsheet, and decoding, and...a lot of unknowns, but we can safely say AMD have an 8 core CPU. Revelation!! So much Excitement! (sarcasm).

It's the first time we're seeing a Zen + Navi codename (last week another codename suggested that 7nm APU Renoir will have a Vega GFX9 GPU), and as @Kaotik mentioned it carries the same 2nd character as the other semi-custom SoCs for gaming consoles.
It says the base clock is 1.6GHz which is a really strong indicator for backwards compatibility for the PS5, and the 8 cores at 3.2GHz tells us a lot on what to expect for CPU performance.

Apart from Phil Spencer making an appearance at AMD's CES presentation to confirm they're working together on the XBox 4, this is probably the biggest palpable news we've had about the next gens, so.. I don't get your unenthusiasm either.

 

[mrcorbo]

It's the first time we're seeing a Zen + Navi codename (last week another codename suggested that 7nm APU Renoir will have a Vega GFX9 GPU), and as @Kaotik mentioned it carries the same 2nd character as semi-custom SoCs for gaming consoles.
It says the base clock is 1.6GHz which is a really strong indicator for backwards compatibility for the PS5, and the 8 cores at 3.2GHz tells us a lot on what to expect for CPU performance.

Apart from Phil Spencer making an appearance at AMD's CES presentation to confirm they're working together on the XBox 4, this is probably the biggest palpable news we've had about the next gens, so.. I don't get your unenthusiasm either.

It's believed that the 1.6 GHz was a arrived at by misinterpreting part of the code. It is now believed that that portion of the code indicates it is a part for Sony given the codes for prior designs.

 

[AlNom]

You know nothing Jon Snow Mr. Corbo.

 

[Esrever]

This is how I read it:
2G = $2000
1600 = 1600 mhz
2C = 2 cores
E8J = Energy 8 Joules
A2 = a two
32 = 32 Compute Units
10/10 = Critics score
13 = unlucky
E9 = better than E8

 

[mrcorbo]

You know nothing Jon Snow Mr. Corbo.

It fits so neatly in with those other Sony chips, though. Ah, well. ES1 naming convention it is.

 

[MrFox]

2C TDP/family means Zen Lite 2, which is the successor of Zen Lite.

You heard it here first.

 

[BRiT]

2C TDP/family means Zen Lite 2, which is the successor of Zen Lite.

You heard it here first.

Zen Lite = Jaguar

Right?

 

[AlNom]

It fits so neatly in with those other Sony chips, though. Ah, well. ES1 naming convention it is.

(sorry, just a pun, it wasn't serious. Will stop now )

 

[mpg1]

It's very well possible that is the code for the PS5 chip....but I don't see how they are extrapolating specs from that. I mean looking at the codes for the PS4/PS4 Pro none of the numbers really correlate to anything other than they are incrementing...

 

[mrcorbo]

(sorry, just a pun, it wasn't serious. Will stop now )

Got me thinking, though, about cognitive biases. I had two equally valid options there based on precedent and chose one based on....nothing really. My wording implied some uncertainty, but not enough.

 

[MrFox]

I have questions:

What are the thermal management considerations of having the processing elements and the memory in such close proximity as opposed to spread out over a wider area?

What is the effect of different package sizes of HBM when it comes to presenting a level surface for good contact with the heatsink? I remember some inconsistencies with the early Vega cards based on from where the HBM2 dies were sourced (or was it where the final GPU was packaged?).

Yes I am very curious to see how the heatsinking will evolve with packages where the thermal requirements are not the same for different chiplets and ram parts. Not a lot of articles about that, surprisingly.

The inconsistencies were probably because it's the early days of 2.5D packaging. The current HBM specs require the stack to be 720um +/-25um. That height is the same regardless of the number of layers. The packaging method would apply and level the protective layer I guess?

The hardest part of cooling is the thermal density on the die itself, the watts per mm2. HBM doesn't raise that at all since it adds more surface to connect additional heat pipes (or vapor chamber contact area).

But the more worrying aspect is that dram in general have much lower thermal limits than logic. So if it's connected to the same heatsink it prevents the main SoC from being allowed higher case temperature. It's a waste of headroom for reducing noise or heatsink mass.

I really think the ideal solution is to have a split heatsink where the ram heatpipes are connected to a colder upstream heatsink, and the SoC heatpipes to a downstream heatsink without any coupling to each other so they can have a different operating temperature. Or... of course... sinking the ram heat through the PCB, and the SoC above, so the bottom heatsink can operate at a lower temperature.

 

[3dilettante]

The inconsistencies were probably because it's the early days of 2.5D packaging. The current HBM specs require the stack to be 720um +/-25um. That height is the same regardless of the number of layers. The packaging method would apply and level the protective layer I guess?

AMD had a slide showing the two variations of Vega's packaging. The difference for the level one, besides having molding material filling the space around the chips, is that the GPU is thinned to the same height as the HBM stacks.
The molding may play a role in the process of thinning the GPU die, or may be needed to provide structural support for the thinner GPU silicon.

Or... of course... sinking the ram heat through the PCB, and the SoC above, so the bottom heatsink can operate at a lower temperature.

At least for now, I do not think the current form of HBM will play along with this. The data paths on the interposer and the base die's solder ball footprint seem to rule out somewhere between two thirds and three quarters of the bottom. The PHY and the straight path the data lines take rule out the almost half of the stack base nearest the GPU, and another quarter or third of the base is power/ground and test pad connections. The remaining area may be able to be put into contact with something, being depopulated probe pads and and test interfacing. At least for the original HBM, this area was allowed to extend past the edge of the patterned area of the Fury interposer and so might be able to be put into contact with non-functional material. Not sure what assumptions were made about the conductivity of what it touches, since it's been non-metal material so far.

That might not be sufficient area for heat transport, and may have mechanical considerations due to there being a mass of metal pressed asymmetrically to the stack. That asymmetry may also mean only a fraction of the DRAM arrays above the metal see thermal benefit, as the lateral conductivity of the stacks isn't great.

 

[DuckThor Evil]

But the more worrying aspect is that dram in general have much lower thermal limits than logic. So if it's connected to the same heatsink it prevents the main SoC from being allowed higher case temperature. It's a waste of headroom for reducing noise or heatsink mass.

I don't think this is an issue at all. The heatsink will not rise to such a temperature that it will be a problem for the RAM even if the SOC runs very hot and a warm heatsink will be enough to cool the RAM. The original AMD Fury Nano has a pretty slim cooling setup and is running at a wattage likely matching or exceeding the next gen consoles. HBM is quite unlikely still imo.

 

[3dilettante]

I don't think this is an issue at all. The heatsink will not rise to such a temperature that it will be a problem for the RAM even if the SOC runs very hot and a warm heatsink will be enough to cool the RAM. The original AMD Fury Nano has a pretty slim cooling setup and is running at a wattage likely matching or exceeding the next gen consoles. HBM is quite unlikely still imo.

HBM is a stack of thermally active dies, which HBM revisions have been gradually improving the dies and how they interact to provide enough heat transport out of the middle. A somewhat warmer top die translates to an incrementally warmer underside that becomes the warmer upper surface of the layer below, and so on. A warm heatsink may be sufficient for the uppermost layers, but each layer below sees increasing temperatures, and it seems like products with HBM will start entering thermal refresh or throttled modes if even one layer starts to hit the their thresholds.

Some Vega boards did have memory temp issues reported sporadically, but that may have been related to the already mentioned non-level packages and the out of spec voltages AMD employed.

 

[AzBat]

I'm very intrigued. Oh my, this soup is delicious, isn't it?

Tommy McClain

 

[Tkumpathenurple]

HBM is a stack of thermally active dies, which HBM revisions have been gradually improving the dies and how they interact to provide enough heat transport out of the middle. A somewhat warmer top die translates to an incrementally warmer underside that becomes the warmer upper surface of the layer below, and so on. A warm heatsink may be sufficient for the uppermost layers, but each layer below sees increasing temperatures, and it seems like products with HBM will start entering thermal refresh or throttled modes if even one layer starts to hit the their thresholds.

In that case, would there be any benefit to including a heatsink on the underside of a PCB without passing through it too? So it needn't interfere with the HBM data paths, but could still cool the lower layers?

Or maybe feed a thermally conductive top layer with both the main, top heatsink, and cascade thermally conductive wires down the sides of the HBM stack to the bottom heatsink too?

I say all of that as a simpleton who knows as much as Jon Snow.

 

[DuckThor Evil]

HBM is a stack of thermally active dies, which HBM revisions have been gradually improving the dies and how they interact to provide enough heat transport out of the middle. A somewhat warmer top die translates to an incrementally warmer underside that becomes the warmer upper surface of the layer below, and so on. A warm heatsink may be sufficient for the uppermost layers, but each layer below sees increasing temperatures, and it seems like products with HBM will start entering thermal refresh or throttled modes if even one layer starts to hit the their thresholds.

Some Vega boards did have memory temp issues reported sporadically, but that may have been related to the already mentioned non-level packages and the out of spec voltages AMD employed.

I just don't think it would be an issue or a significant technical challenge in a console environment. A proper active cooled heat sink wouldn't reach temperatures high enough to cause problems with the HBM cooling as the heatsink will still be at a much lower temps than the SOC.

 

[liolio]

I believe more and more that SOny should wait for the PS5. I've a gut feeling that personal graphic hardware is about change in the upcoming years, unified shader architectures are going the way of dodo. I'm not sure about where the last push will come from but it will come.
Sony needs to catch-up with MSFT great efforts on backward and forward compatibility and overall emulation before jumping into the next gen (as well as assess further where hardware is going or when the next shift is going to happen). In my opinion Sony should release a last PS4 SKU, closer in specs to the original PS4 than to PRO meant to be cheap to produce (target retail price 249€).
While they have that they shold try to flood the market with it as well as classic/cheap games till they feel comfortable jumping into the next gen.

As for MSFT there are a lot of noises and whatever is true or not wrt rumors it seems they made their call already.

 

[del42sa]

https://twitter.com/TUM_APISAK

NAVI Lite @ 1,8GHz ?

 

[vipa899]

Lite meaning midrange/low power?