Next Generation Hardware Speculation with a Technical Spin [2018]

[Shortbread]

The question that should be asked: What will constitute a mid-end AMD gaming PC spec-wise in 2020? Then we should have a better understanding or reality of what to exspect from the next generation of consoles. Not so much matching it (mid-end PC) spec-for-spec, but the performance deltas that Sony/MS machines should be reaching for or slightly above.

Hypothetical mid-end AMD spec PC for 2020....
CPU: 3.2GHz 8c/16t processor
GPU: 12TF/32FP with 8GB VRAM
Ram: 16GB of DDR5 or DDR6
Storage: 1TB SSD
Pricing: $899-$999 (depending on retailer, vendor, manufacturer, etc.)

Hypothetical 2020 console possibly being...
CPU: 3GHz 8c/16t processor
GPU: 14TF/32FP
Shared Memory Architecture: 16GB GDDR6
Storage: Hybrid solution of 1TB mechanical storage with 128GB (or 256GB) solid-state memory caching/paging.
Pricing: $499

 

[Xbat]

Hypothetical 2020 console possibly being...
CPU: 3GHz 8c/16t processor
GPU: 14TF/32FP
Shared Memory Architecture: 16GB GDDR6
Storage: Hybrid solution of 1TB mechanical storage with 128GB (or 256GB) solid-state memory caching/paging.
Pricing: $499

I feel this is what what will happen. Maybe slower clock on the CPU and maybe closer to 12 TFlops GPU.

The dream is 15TFlop GPU though.

 

[anexanhume]

I feel this is what what will happen. Maybe slower clock on the CPU and maybe closer to 12 TFlops GPU.

The dream is 15TFlop GPU though.

The question is clocks. If they opt for a PS4/Pro type clocking approach, I think we’ll end up 10-12TF based on shrink estimates for 7nm, assuming a similar die size and allocation of space to the PS4.

If they go for a Xbox One X type clocking, cooling, and power delivery approach, I think we’re looking at 12-14TF. The question is whether the XB1X is seen as something that can be produced economically for the mass market.

If they go crazy and opt for a fully discrete GPU, maybe we could reach 15TF. That gets us an 8x scaling over PS4.

 

[Deleted member 13524]

If they go crazy and opt for a fully discrete GPU, maybe we could reach 15TF. That gets us an 8x scaling over PS4.

There are very few reasons to do discrete CPU+GPU and too many setbacks.

An 8-core Zen 2 module plus L3 at 7nm will be what, 50mm^2?

Discrete GPU would mean increased CPU-GPU latency, a bunch of I/Os that would need to be repeated on each side, developer transparent UMA would be much more difficult to adopt, etc.

 

[anexanhume]

There are very few reasons to do discrete CPU+GPU and too many setbacks.

An 8-core Zen 2 module plus L3 at 7nm will be what, 50mm^2?

Discrete GPU would mean increased CPU-GPU latency, a bunch of I/Os that would need to be repeated on each side, developer transparent UMA would be much more difficult to adopt, etc.

I think 8 core Zen 2 with L3 will be closer to 100mm^2 based on Zeppelin CCX sizing and known 7nm scaling factors. There will likely be some core growth in terms of transistors and cache increases to bump it up.

 

[MrFox]

I think 8 core Zen 2 with L3 will be closer to 100mm^2 based on Zeppelin CCX sizing and known 7nm scaling factors. There will likely be some core growth in terms of transistors and cache increases to bump it up.

But the complete zeppelin ccx, at 213mm2 on 14nm, includes memory controllers, pcie, and ifop, all the external phy which are required for a standalone part, which leaves about half the area for the actual cpu?

 

[anexanhume]

But the complete zeppelin ccx, at 213mm2 on 14nm, includes memory controllers, pcie, and ifop, all the external phy which are required for a standalone part, which leaves about half the area for the actual cpu?

Two CCX would be about 88 mm^2, according to wikichip. Some of those IP blocks will need to be kept as well.

https://en.wikichip.org/wiki/amd/microarchitectures/zen#Modules_.28Zeppelin.29

 

[BRiT]

But the complete zeppelin ccx, at 213mm2 on 14nm, includes memory controllers, pcie, and ifop, all the external phy which are required for a standalone part, which leaves about half the area for the actual cpu?

But all that would be required for the Discrete GPU rumored specifications, right?

 

[mrcorbo]

The question that should be asked: What will constitute a mid-end AMD gaming PC spec-wise in 2020? Then we should have a better understanding or reality of what to exspect from the next generation of consoles. Not so much matching it (mid-end PC) spec-for-spec, but the performance deltas that Sony/MS machines should be reaching for or slightly above.

Hypothetical mid-end AMD spec PC for 2020....
CPU: 3.2GHz 8c/16t processor
GPU: 12TF/32FP with 8GB VRAM
Ram: 16GB of GDDR5 or GDDR6
Storage: 1TB SSD
Pricing: $899-$999 (depending on retailer, vendor, manufacturer, etc.)

Hypothetical 2020 console possibly being...
CPU: 3GHz 8c/16t processor
GPU: 14TF/32FP
Shared Memory Architecture: 16GB GDDR6
Storage: Hybrid solution of 1TB mechanical storage with 128GB (or 256GB) solid-state memory caching/paging.
Pricing: $499

GDDR5 or 6 as main memory in a PC?

Also, you can't consider memory specs without including bandwidth in those considerations. 16GB of GDDR6 pretty much guarantees a 256-bit memory interface which probably puts your bandwidth somewhere in the neighborhood of 500 Gb/s depending on the $$$/heat and power budget allocated for memory. 12GB of GDDR6 pretty much guarantees a 384-bit memory interface and could get you somewhere in the vicinity of 700 GB/s of memory bandwidth. Choose one. Higher capacity or higher bandwidth. You can't have both.

 

[MrFox]

Two CCX would be about 88 mm^2, according to wikichip. Some of those IP blocks will need to be kept as well.

https://en.wikichip.org/wiki/amd/microarchitectures/zen#Modules_.28Zeppelin.29

But all that would be required for the Discrete GPU rumored specifications, right?

They don't need much other than a single inter processor channel (this one has three?) no memory controllers since it would be unified, and there is no need for more than 4 pcie lanes for peripherals on a console. Maybe 75mm2 ???

If it ends up making a 300mm2 gpu plus a 75mm2 cpu, might as well make a single 350mm2 integrated part without the overhead.

 

[Shortbread]

GDDR5 or 6 as main memory in a PC?

Also, you can't consider memory specs without including bandwidth in those considerations. 16GB of GDDR6 pretty much guarantees a 256-bit memory interface which probably puts your bandwidth somewhere in the neighborhood of 500 Gb/s depending on the $$$/heat and power budget allocated for memory. 12GB of GDDR6 pretty much guarantees a 384-bit memory interface and could get you somewhere in the vicinity of 700 GB/s of memory bandwidth. Choose one. Higher capacity or higher bandwidth. You can't have both.

Meant DDR for PC, more specifically DDR5 for a 2020 mid-spec PC. And I'm going with 16GB GDDR6 memory configuration for now, with a 2020 console (although I'm pulling for 24GB GDDR6 in my dreams).

 

[mrcorbo]

Meant DDR for PC, more specifically DDR5 for a 2020 mid-spec PC. And I'm going with 16GB GDDR6 memory configuration for now, with a 2020 console (although I'm pulling for 24GB GDDR6 in my dreams).

So, for you, capacity over bandwidth. Why?

 

[Shortbread]

So, for you, capacity over bandwidth. Why?

I rarely hear developers state, "their bandwidth starved," but wanting more memory for all sorts of reasons. Plus, I'm not 100% sure Sony (MS possibly as well) will be using a traditional PCI express busing system to tie into the memory controller/interface as we know it. There could be a possibility where AMD's Infinity Fabric technology, more specifically it's "Infinity Scalable Data Fabric," can be used to tie in multiple unified memory controllers interfaces, independently, but in a unified fashion. Meaning; a dual 256-bit memory interface (i.e., 8GB GDDR6 per memory interface, if 16GB DDR6 is the flavor next-gen systems are aiming for) can be used in a unified fashion, rather than having all the memory modules tied into a single 256-bit memory interface.

 

[mrcorbo]

I rarely hear developers state, "their bandwidth starved," but wanting more memory for all sorts of reasons. Plus, I'm not 100% sure Sony (MS possibly as well) will be using a traditional PCI express busing system to tie into the memory controller/interface as we know it. There could be a possibility were AMD's Infinity Fabric technology, more specifically it's "Infinity Scalable Data Fabric," can be used to tie in multiple unified memory controllers interfaces, independently, but in a unified fashion. Meaning; a dual 256-bit memory interface (i.e., 8GB GDDR6 per memory interface, if 16GB DDR6 is the flavor next-gen systems are aiming for) can be used in a unified fashion, rather than having all the memory modules tied into a single 256-bit memory interface.

I don't know what you mean by "traditional PCI express busing system to tie into the memory controller interface". Dual 256-bit memory buses connected to 16 GB of memory would necessitate 16(!) memory chips on the motherboard. So, is it your belief that there will be a discrete CPU and GPU each with their own 8GB of memory on a 256-bit bus and those two memory controllers will be connected over Infinity Fabric or ?????

 

[Shortbread]

I don't know what you mean by "traditional PCI express busing system to tie into the memory controller interface". Dual 256-bit memory buses connected to 16 GB of memory would necessitate 16(!) memory chips on the motherboard. So, is it your belief that there will be a discrete CPU and GPU each with their own 8GB of memory on a 256-bit bus and those two memory controllers will be connected over Infinity Fabric or?????

I'm more inclined to believe that PS5 will have a discrete design (CPU and GPU), both having access [unified fashion] to the total pool of memory, all tied through Infinity Fabric / Infinity Scalable Data Fabric technology. I'm not 100% sure how the design (motherboard, logic, controllers, etc.) will be laid-out or how it truly works. But I'm willing to bet that Sony is going for a more robust-bespoke design (not exotic, but more complex design) with PS5 hardware, more so than PS4 design.

 

[mrcorbo]

I don't know what you mean by "traditional PCI express busing system to tie into the memory controller interface". Dual 256-bit memory buses connected to 16 GB of memory would necessitate 16(!) memory chips on the motherboard. So, is it your belief that there will be a discrete CPU and GPU each with their own 8GB of memory on a 256-bit bus and those two memory controllers will be connected over Infinity Fabric or ?????

To add a little context to the bandwidth discussion:

Vega64's 12.7 TFlops are supported by 483.8 GB/s of memory bandwidth for it's own exclusive use (no sharing with the CPU)

Doing the math that's ~38.1 GB/s of memory bandwidth per TFlop.

For a 14TF target in a console then, if you were to directly scale this, you would want 533 GB/s *plus* some additional bandwidth for the CPU to use. Ryzen 2700 and its 8 cores and 16 threads is spec'd to use 46.8 GB/s (I think, someone correct me if I calculated that ) with it's dual channels of DDR4-2933 and supports (and benefits from) faster RAM than that.

 

[mrcorbo]

I'm more inclined to believe that PS5 will have a discrete design (CPU and GPU), both having access [unified fashion] to the total pool of memory, all tied through Infinity Fabric / Infinity Scalable Data Fabric technology. I'm not 100% sure how the design (motherboard, logic, controllers, etc.) will be laid-out or how it truly works. But I'm willing to bet that Sony is going for a more robust-bespoke design (not exotic, but more complex design) with PS5 hardware, more so than PS4 design.

If you're going to be this hand-wavy about details than there's not much to discuss, really.

 

[Shortbread]

Because I don't know anything about the PS5!?

I'm just providing some speculation and random thoughts on the possible technology it may use. And yes, I may have a limited scope on how all the technology (like infinity fabric) works within conjunction with other logic... but that doesn't mean I'm totally on another planet without some understanding of it's possibilities . If I'm lite on other details, it's simply that I'm learning more on what's possible with today's and tomorrow technology. So if I'm hand-wavy, that's fine, I'm in the right thread on doing so.

 

[vipa899]

So if I'm hand-wavy, that's fine, I'm in the right thread on doing so.

Your dreaming and thats whats exactly in the topic title. Just hoping those dreams wont get shattered when realistic specs drop, even though i hope ps5 will be high end hw it will probally be mid end at best like last time (and all other times).

Going to be intresting to see what ND can do with modern hardware.

 

[Entropy]

To add a little context to the bandwidth discussion:

Vega64's 12.7 TFlops are supported by 483.8 GB/s of memory bandwidth for it's own exclusive use (no sharing with the CPU)

Doing the math that's ~38.1 GB/s of memory bandwidth per TFlop.

For a 14TF target in a console then, if you were to directly scale this, you would want 533 GB/s *plus* some additional bandwidth for the CPU to use. Ryzen 2700 and its 8 cores and 16 threads is spec'd to use 46.8 GB/s (I think, someone correct me if I calculated that ) with it's dual channels of DDR4-2933 and supports (and benefits from) faster RAM than that.

Adding to your context, many of the problems I’ve faced professionally have working sets that are way larger than cache, and typically end up being bandwidth bound. That makes for lousy benchmarketing unfortunately (as opposed to tiny working sets and little to no data dependency). CPUs can benefit from way more bandwidth than is supplied via typical PC systems. Expandable bandwidth costs money though.

CPUs often have other access patterns than GPUs, more random cache misses and requiring less data to be fetched (fetch too much and you’re just needlessly blocking the bus and flushing the cache with useless data) meaning that CPU and GPU step on each others toes. There have been graphs floating about on this issue as observed on Sony consoles, but the problem is inherent in a shared memory setup.

In short, when it comes to bandwidth in a console shared memory system you want more of it than the sum of the split pool values would suggest. But even in a non expandable system, bandwidth carries real costs.