New Memory Interface for R5x0...

IIRC if you the core size goes down ~50% if transistor count remains the same when moving from 130nm to 90nm

 

Advanced Memory Interface, akin to AMD's HT maybe?

 

If ati pushed a 512 bit bus, I would also be surprised seeing as they're still using 128 for the low end. And I'm guessing that was a cost-based decision?

 

When Dave objected against 512bit, I thought the same as he said later. Smaller core doesn't jive with adding lots of pins.

And then I went in the other direction. First thought was Yellowstone (as Mariner said), but that interface never made it AFAIK. At least not to any memories. But RAMBUS now tries to sell another bus called XDR DRAM. I don't think it's just a rebranded Yellowstone.

However I doubt that that's it. Not realy for any technical reasons, but because RAMBUS isn't "kosher". (How's that for a good reason. )

I believe more in Xmas' proposition. "Advanced memory interface" == "full memory virtualization".

 

How about dual 4 channel controlers each servicing 1/2 the Quads.

How about a much bigger on die Cache servicing the controler.

 

Which of course makes the top end design scalable to the midrange and lowrange and far as functionality goes.

1/2 the Quads and one Controller for the mid range.

1/4 the Quads and one Controller for the low end.

 

Wouldn't full memory virtualization cut out the need for two dedicated sets of memory for individual processors on a multi-processor graphics board?

If that were the case it would make building a dual-core board far more cost effective and a much simplified layout. It would also certainly be more cost effective than the costs involved in an SLI setup, even if your system already had an SLI capable motherboard.

 

In regards to the people talking about on-die cache, it's possible they could use the Mosys (?) embedded ram like ArtX/ATI used in the Gamecube. Their engineers already have experience with it and if memory serves, the Mosys design used a single transistor to create an SRAM cell instead of the standard three transistors. I dunno how the Mosys design is performance wise these days compared to other options. Now... back to my quiet B3D lurking.

 

Are they building a little CPU in their GPU?

 

My guess is GDDR-4. Last time around ATI worked with Micron sorting out the issues with GDDR-3, and since then ATI got the X-Box 2 contract which included them designing the memory interface.

The GDDR-4 ecosystem might reflect a lot of Rambus XDR positive qualities.

 

Well there are a couple ways to interpret this:

A move away from unified memory for vertex, textures, and buffers.

Enhancements to the internal interfaces between the various on-chip requesters and the memory controller. Maybe something to deal with the NxM complexity issue.

Maybe breaking the memory into difference interfaces using different dram technology. There is little point in buying 1GB of ultra high speed dram just to handle textures.

Different memory controller logic employing deep re-ordering capabilities

Different memory technology, increasing bandwidth per pin.

In the end I don't see them breaking up the memory space into seperate interfaces and part because of the complications that can entail.

Aaron Spink
speaking for myself inc.

 

Lots of transistors and roughly the same number of pins. Unless they got some of Intel's BBUL magic.

So, I'm thinking maybe an increment in the memory used, GDDR-4. And possibly a memory array on die.

As for clients, that could very well be a reference to the framebuffer.

 

Can be this ?

http://theinquirer.net/?article=18556


I know it is The Inquirer but...

 

I hope they use magnetic transistors (?) to achieve this.

 

Thats good speculation.

http://www.eet.com/story/industry/semiconductor_news/OEG20010111S0021

So this Quad Band Technology is different from how Rambus achieves high data rates, and it can be applied to flash memory. There has already been speculation that the Xbox 2 will have a flash drive instead of a hard drive. Right now with XDR, Rambus is at an octal rate.

 

i rly am curious as to what the r520 will actually end up offering. i dont think its nearly as big of a jump as alot of people seem to think.

 

R520 will be SM3, that's 100% sure.

 

I think they already have that kind of caches, made of sram.

pixel and vertex shaders are really small - we are talking about 1024 instructions limits, if one instruction is 32 bits the whole "big program" takes 4k. AFAIK some "avarage program" still is something like 10-20 instructions -> 40 - 80 bytes.

 

http://www.xbitlabs.com/news/memory/display/20040629105414.html

So QBM-2 is scheduled for 2005, which is based on DDR-II.