New Memory Interface for R5x0...

[Dave Baumann]

Goldman believes ATI set to launch new architecture in 1H05 includes SM03, advanced memory interface relatively smaller die size 90nm

Speculations if you please...

 

[Bouncing Zabaglione Bros.]

512 bit? As memory speeds are currently doing a lot of the bottlenecking, the only other choice is to increase bandwidth. ATI surprised us with early adoption of 256 bit interface with R300 when Nvidia were telling us it wasn't necessary, so maybe they've taken the same route this time around.

 

[Dave Baumann]

Actually, read the rest of that quote carefully.

 

[Bouncing Zabaglione Bros.]

Actually, read the rest of that quote carefully.

How about you give us the URL for the source of the quote so we can see the full context?

 

[Vadi]

Seems easy now after seeing the SLI results. Ati may do something against the memory bottleneck. An on-die memory controller along with some sharing ala SLI I'd guess.


edit: Bouncing Zabaglione Bros. beat me to it!

 

[Lezmaka]

An on-die memory controller along with some sharing ala SLI I'd guess.

Ummm, doesn't pretty much every graphics chip have an on-die memory controller?


Anyway, couldn't it just be the HyperMemory/virtualization stuff? And I'm assuming where it says SM03 in the quote is supposed to be shader model 3.0?

 

[Vadi]

Ummm, doesn't pretty much every graphics chip have an on-die memory controller?

Oops, yes.

 

[AlNom]

Is that quotation a translation of something?

Goldman believes ATI is set to launch a new architecture in 1H05 ,which includes SM03, an advanced memory interface, a relatively smaller die size 90nm ...

what is "relatively" supposed to mean? Isn't 90nm smaller than 130nm by default :?

 

[Fodder]

what is "relatively" supposed to mean? Isn't 90nm smaller than 130nm by default :?

The process will shrink but the die won't be much smaller due to higher transistor counts? I think there should be another comma between die size and 90nm.

 

[Mariner]

Goldman believes ATI set to launch new architecture in 1H05 includes SM03, advanced memory interface relatively smaller die size 90nm

Speculations if you please...

Erm, Yellowstone?

 

[991060]

Why nobody said on-die cache? I mean an explicit one, not those already deploied between pipeline stages now days. A 10MB edram is said to be inlcuded in the XBOX next GPU, I wouldn't be surprised if finding the same thing on the desktop variant.

 

[Neeyik]

Why nobody said on-die cache? I mean an explicit one, not those already deploied between pipeline stages now days. A 10MB edram is said to be inlcuded in the XBOX next GPU, I wouldn't be surprised if finding the same thing on the desktop variant.

I was just about to post the very same thing. I suspect that Dave was pointing out the "relatively smaller die size" in answer to the earlier speculation of a 512-bit bus. A wider bus couldn't really be described as being advanced, but having something that prefetches into a L2-type-of-cache might be.

 

[Xmas]

Embedded memory is a possibility, but I think the advanced memory interface rather means full memory virtualization. I don't think 512bit is viable option yet (though I think we might see cards with 384bit bus in the future).

 

[Pete]

Embedded as on on-package, not on-die, right? (Like the P2's or whatever had off-die cache running at a lower clock.) I'm not sure how RAM embedded on the die would result in a smaller die, unless GPUs require a small amount of it (256-512K?).

If it's virtualized memory, we won't be seeing many benefits for a while, no?

 

[Dave Baumann]

The point about the die size is that, while process shrinks the pads don't - a slightly smaller physical die size doesn't lend itself to more connections (hence pads), so I would guess at external physical bus widths being similar.

However, while the die size is said to be slightly smaller, at 90nm things are relatively going to be much larger (no# of transistors in relation to die size). Something you might want to think about is what issues there might be with the current memory busses in chips as the complexity, hence relative sizes increase.

 

[cristic]

Couldn't a small amount of embedded ram be used as a cache for pixel and vertex shader programs ? I.e. minimizing the penalty of loading them from onboard memory... i mean a shader are smaller then textures.

please ignore if i#m talking crap, this domain is new to me

 

[Pete]

Perhaps I'm overestimating cache die space considering the huge transistor counts of current GPUs vs. CPUs. In fact, anyone know off-hand how the 90nm P4EE 2MB compares to the 130nm NV40 in terms of transistors and size?

 

[Tim]

Perhaps I'm overestimating cache die space considering the huge transistor counts of current GPUs vs. CPUs. In fact, anyone know off-hand how the 90nm P4EE 2MB compares to the 130nm NV40 in terms of transistors and size?

1MB cache is 57 mio. transistors + redundency (cache is SRAM). 1MB embeded DRAM would only be 9.5 mio. transistors.

The P4EE is still made on the 130nm process.

 

[vb]

I know i'm gonna get killed here, but what about Rambus?

128 bit rambus would be overkill bandwith wise and latency should be well compensated by inherent parallelism...

VIA also had some "Quad band" tech...

 

[991060]

However, while the die size is said to be slightly smaller, at 90nm things are relatively going to be much larger (no# of transistors in relation to die size). Something you might want to think about is what issues there might be with the current memory busses in chips as the complexity, hence relative sizes increase.

a few separated memory interfaces with each connecting to a processing unit(maybe quad) in the chip? I'm just guessing...