"Nerve-Damage"
Regular
Jaws said:Yep, you're wrong.
Agree to disagree there!!
I've shown you TWO block diagrams from E3 2005.
You showed me two diagrams with the RSX to Cell and the CPU to South Bridge, and the IO devices to the South Bridge. But that doesn’t explain the data between the South Bridge and the IO devices.
Again, the I/O devices DO NOT directly connect to CELL. They connect to SB. It's the SB that connects to CELL with FlexIO. The 6 UNIVERSAL_SERIAL_BUS devices connect to the SB, with their own busses. Your links have confused what FlexIO is. It's the equivalent of PCI-E. The PCI-E bus isn't going to replace USB nor is FlexIO, but they work together. This is basic stuff.
Everyone is wrong except you? I got it!!
Lets use another angle. COMMON SENSE.
I say 40 GB/sec. You say 76 GB/sec.
76-40 = 36 GB/sec
There's no way that the HDD, network, Blu-ray, USB devices etc. are going to need MORE bandwidth (36 GB/sec) than CELL-RSX (35 GB/sec). I'm repeating myself now, so you can believe what you want if that makes you happy...
Who are you judge bandwidth waste? Are basing your opinion off PC standards and how they interact with each other? Consoles are built in-mind for high bandwidth needs, not what today’s standards maybe, it’s the future applications they are worried about.
So by your logic; data rates between IO devices and South Bridge wouldn't ever or never change. Meaning 5-10 years later we will still be using the same equivalent data transfer among the IO devices connecting to south bridge (or another chip).
Anyhow, January or February everything will be settled………..
Last edited by a moderator: