More hits to the heart for the 4 PE's CPU fans (CELL)

[Panajev2001a]

Few more details about the CELL processor continues to dribble out. Unfortunately nothing about the programming model and programming environments that IBM/Sony will promote/recommend.

If I have time, I'll write up some of this as a "part 2" to the CELL article, although that may not happen. Regardless, there are a few new details that I believe are "new" as far as the CELL processor goes, or I simply missed the discussion at ISSCC.

1. The CELL processor will natively support glueless 2 way SMP. N Way SMP for N > 2 needs a coherent switch. Glueless SMP ring is not possible

2. SPE dynamically reconfigurable as secure processor.

3. Locking caches (via replacement Management tables)

4. DMA is fully Power Arch Protect/x-late

5. Direct programmer control DMA/DMA-list

http://realworldtech.com/forums/ind...&Thread=1&entryID=46582&roomID=13

A 4-way PE's system gets more complicated: I do not recall a coherent switch in the original patent by Suzuoki Masakazu.

 

[McFly]

I think I can life with a 2 PE + NvGPU setup, thx.

Fredi

 

[one]

Isn't it because it has only one interface in the processor? Still, the SMP by 2PE + 2PE is OK without a bridge, if your power consumption budget is limitless, that is.

 

[cthellis42]

I'm still picturing people sticking chips together with Elmer's from that first comment...

 

[nAo]

4. DMA is fully Power Arch Protect/x-late

What does that mean?

5. Direct programmer control DMA/DMA-list

We already know that from latest IBM+Sony patents

 

[Panajev2001a]

4. DMA is fully Power Arch Protect/x-late

What does that mean?

5. Direct programmer control DMA/DMA-list

We already know that from latest IBM+Sony patents

Well at least the patents hunt was useful and worth the time it took .

As for the first... hopefully Google is our friend.

 

[cthellis42]

Of course Google is our friend! Would anyone but a friend deliver so much porn to us?

 

[London Geezer]

Of course Google is our friend! Would anyone but a friend deliver so much porn to us?

You get porn from google??? man there's so many better places...

 

[Quaz51]

Dual-Cell or not Dual-Cell?

 

[London Geezer]

Dual-Cell or not Dual-Cell?

That's a single one.

 

[version]

what is that between CELLS?

 

[MfA]

It is 1:1 with the cells, if it was part of a dual cell setup it would be 1:2.

 

[London Geezer]

You asked that already on another thread and it was answered. Can't remember to be honest but it was something about "control".. errr i really can't remember, it was nothing major though.

 

[Quaz51]

You asked that already on another thread and it was answered. Can't remember to be honest but it was something about "control".. errr i really can't remember, it was nothing major though.

i never see that on another wafer (> google image > wafer)

 

[version]

this is G5 wafer, and nothin extra circuit, on cell's wafer why? and why pair?

 

[Quaz51]

It is 1:1 with the cells, if it was part of a dual cell setup it would be 1:2.

it is 1:2

 

[London Geezer]

Pair what?

 

[version]

Pair what?

extra circuit with 2 cell

 

[London Geezer]

It's not part of Cell. This was answered already, i think it had to do with testing and stuff. Obviously there is a lot of testing to be done at this stage, maybe that's the reason these early wafers have those extra circuits.

 

[Quaz51]

intel P4 wafer