Mali200 from Falanx - new challenger for desktop markets or pure utopia?

[Ailuros]

Is there any information floating around on what exactly Falanxes "partially deferred" rendering scheme entails? IIRC, PowerVR supports something which may be similar
(reserving a fixed size buffer for tile lists and rendering them on overflow).

From prior whitepapers it seems like a tile based renderer with early-Z . Not good enough I know.

PowerVR has a macro/micro tiling patent and on the SGX diagram there's a macro tiling engine being mentioned. I don't know if there's a fixed size of a tile buffer in those designs, the patent just mentions that an upper threshold of macro tiles for the display list can be set and could be at around 75% or any other value. From what I remember macro tiles can be processed in parallel.

SGX and Mali200 appear to be worthy contenders for eachother - kudos to PVR and Falanx for designs that are much more interesting/innovative than what we're seeing in the highend desktop segment (now if only we could get some more info on them ).

It's always nice to see more tilers that's true

 

[Ailuros]

As long as PowerVR is the only one who is doing TBDR they shall remain untouchable in this mobile realm.

Anybody can do TBR, anybody can do it via developing their own methods by not touching img patents, but you have to realize TBDR is where the real magic happens, this is where PowerVR is set apart and make no mistake this has been succesfully patented worldwide.

This reason and this reason alone is why nobody shall be able to touch Img and it's PowerVR line from total domination of the entire scene.

Do you even realize that a wider deployment of tile based accelerators would be of actual benefit for IMG/PowerVR and of course any other companies that deal with similar approaches?

Also did it ever hit you that a combination of early-Z (which is in effect what one could call application driven deferred rendering) and 4-level hierarchical Z-buffering (and other possible optimisations) might eventually have benefits too?

 

[psurge]

So you think the heirarchical Z/stencil buffers are used as geometry is streaming in to stop completely occluded triangles/vertices from being stored in the tile lists? What gets me is the statement that the algorithm operates in a "fixed memory budget with no performance loss".

I assume this refers to the PVR approach of rendering partially complete tiles once the allocated tile list memory is overflowed.

Assuming the Falanx HZ occlusion culling were perfect and all triangles were opaque, I suppose a tile couldn't be influenced by more than S*3 vertices (where S is the # of samples in the tile). So, barring translucency, this would in fact require a fixed amount of memory per tile. The worst case is still ridiculous though so AFAICT there are 2 explanations : I'm taking a statement on a marketing slide way too seriously, and the HZ + tile list approach means that a reasonably sized tile list buffer is almost never overflowed in practice, or they are doing something really clever instead of/in addition to the above.

 

[Ailuros]

So you think the heirarchical Z/stencil buffers are used as geometry is streaming in to stop completely occluded triangles/vertices from being stored in the tile lists? What gets me is the statement that the algorithm operates in a "fixed memory budget with no performance loss".

Merely a guess but yes it could be. It would be interesting to see what the similarities and differences to PowerVR's approach are, since theirs occlude geometry too.

I assume this refers to the PVR approach of rendering partially complete tiles once the allocated tile list memory is overflowed.

That happened IMO several generations ago; if ever of course.

Assuming the Falanx HZ occlusion culling were perfect and all triangles were opaque, I suppose a tile couldn't be influenced by more than S*3 vertices (where S is the # of samples in the tile). So, barring translucency, this would in fact require a fixed amount of memory per tile. The worst case is still ridiculous though so AFAICT there are 2 explanations : I'm taking a statement on a marketing slide way too seriously, and the HZ + tile list approach means that a reasonably sized tile list buffer is almost never overflowed in practice, or they are doing something really clever instead of/in addition to the above.

In usual practice it won't overflow on any tile based architecture; they're always the corner cases people usually refer to. Gigapixel's architecture might have been quite similar, since they had a Z-buffer too.

What I find highly interesting is that they have a 4 level hierarchical Z-buffering scheme, whereby ATI's approach consists of 3 levels.

 

[Nappe1]

As long as PowerVR is the only one who is doing TBDR they shall remain untouchable in this mobile realm.

Anybody can do TBR, anybody can do it via developing their own methods by not touching img patents, but you have to realize TBDR is where the real magic happens, this is where PowerVR is set apart and make no mistake this has been succesfully patented worldwide.

oh my... am I really looking at myself three years ago? was I this pathetic, really? I do know that I was (and still I am) a rather enthuastic fan boy, but did it look this bad outside?


krmh... back to topic,
as long as it's from this world designed by human being, there will be another human being surpassing it sooner or later. There's no Real Magic. It's all based on scientific reseach and how things really work. badly done TBDR (not that PowerVR would have one nor I would have anything against alternatives to IMR) is going to be as bad as bad IMR. TBDR isn't holy grail of hw graphics acceleration that would make bad product as unbeatable.

 

[Ailuros]

TBDR isn't holy grail of hw graphics acceleration that would make bad product as unbeatable.

You'll have a hard time seeing me claiming that TBDR is a complete eulogy and IMRs a complete panacea. As with all things there are advantages and disadvantages and this is true for both architectures. What counts is what comes out at the other end.

IHVs will do the best they can within a specific timeframe to improve efficiency; however in embedded/UMA based devices TBDRs have an advantage and that's the reason why I expect an explosion of tile based/early-Z based accelerators for those markets soon. Since this comes down as to which device burns more bandwidth, you'd have to find the corner cases of each architecture, factor in the normal bandwidth consumption under usual conditions and then you might find an average where you can see which can spit out the highest efficiency.

TBDRs have a huge advantage with floating point framebuffers and this hasn't been completely proven yet. Take a scene with let's say 200 shader instructions (vertex/pixel/geometry) in an X resolution with 4xAA and 64bpp HDR and we'll see then if the often claimed parameter bandwidth problem really works against DR in the end. Even more so in a unified shader architecture.

 

[Gollum]

Leave it to the Scandinavians to pull the proverbial bunny out of a hat. Interesting stuff! Amazing how, once again, a small company of university graduates manages to come up with quite impressive looking technology. Isn't everybody constantly saying how current 3D technology is so complicated, it'd take teams of hundreds of engineers to design a chip with all the latest features? Sure, no VS, but PS beyond SM3.0 certainly isn't simple either.

The scalability looks like it could be a novel and effective way to satisfy many different demands. I don't expect it'd scale up to the power of desktop graphics chips by Nvidia or ATI anytime soon though. Pitty, I'd appreciate the variety, would make following the desktop market more interesting again! Whatever market they're in, good to have a new face in the game.

 

[_xxx_]

Leave it to the Scandinavians to pull the proverbial bunny out of a hat.

So that means we need more blonde beauties everywhere as a motivation?

 

[Ailuros]

So that means we need more blonde beauties everywhere as a motivation?

It rather means that there are strict restrictions to alcohol consumption

 

[_xxx_]

It rather means that there are strict restrictions to alcohol consumption

Wouldn't matter as long as the babes are there

 

[Mariner]

Actually when I've been Scandinavia it's more of a 'strict restrictions to alcohol purchase'. They seem to manage the consumption part without too many problems!

 

[_xxx_]

We smug..., err, imported our own stuff into the country from Germany

 

[Ailuros]

The scalability looks like it could be a novel and effective way to satisfy many different demands. I don't expect it'd scale up to the power of desktop graphics chips by Nvidia or ATI anytime soon though. Pitty, I'd appreciate the variety, would make following the desktop market more interesting again! Whatever market they're in, good to have a new face in the game.

Assuming a scaled version of that architecture would make it into integrated graphics and the efficiency would be as high as they promise, I could under circumstances see some pressure from the very low end of the market.

If a company manages to squeeze into an IGP as much performance as in ultra low-end GPUs of the future, the latter will have to gain more in performance to justify their existence. Same would be true for notebook IGPs.

 

[hkultala]

Mali 200 does not contain a VGA core, so if we just put that to PC, we either

a) do not get any graphics at bootup/bios/os install or if we have a driver problem

b) have to put some VGA core from elsewhere to the same chip

 

[Arun]

b) have to put some VGA core from elsewhere to the same chip

Welcome to the IP market

Assuming a scaled version of that architecture would make it into integrated graphics and the efficiency would be as high as they promise, I could under circumstances see some pressure from the very low end of the market.

Probably not in that timeframe imo; the integrated 6200TC on the C51 isn't going to change much either. Would it be a big boost to Falanx? Yeah, probably. Would it be a big hit on the duopoly? Hardly. IMO, at least.

Uttar

 

[Ailuros]

IGPs are more in the direction of a monopoly these days, if you consider Intel's marketshare.