Interesting interview with IBM (Cell, backwards compatability...)

[Gubbi]

I have a (maybe stupid) question.
On 7-SPE cells, will there be a difference when f.e. 1 cell has SPE nr.1 disabled and another one has nr.4 disabled as they are connected to a ring bus ?

It shouldn't have any consequence what so ever. If SPE 4 is disabled, SPE 3 and 5 will be neighbours for all intents and purposes (SPE 4 will never produce traffic/contention on the bus), same way with any other SPE.

Cheers

 

[Crossbar]

Look at DD2 as I posted ealier:

http://www-03.ibm.com/chips/photolibrary/photo10.nsf/WebViewNumber/ED994790FAECFD6900256FEA0062126B

Fours, not fives. At the bottom right under options, there's the option to download the full high resolution version of the picture.

Jawed

Damn!!!!

Then it must be DD3 or whatever version they have by now.

There may of course also be some redundancy within the "fours", even though I guess the bulk is made up by the floatingpoint units. From the picture you can also see that not everything is organised in fours.

Nevermind, but I still believe teh SPEs are strong candidates for logic redundancy due to their highly parallel architecture if someone were to implement it.

 

[Carl B]

Well, they did say the move from DD2.x to DD3.x was for yields, didn't they? So perhaps the intra-unit redundancy is in play afterall.

Who knows... Reeves needs some lessons in unambiguous interviewing.