Interesting interview with IBM (Cell, backwards compatability...)

[RobertR1]

The cell is in yield hell?

Who soaks up the costs of failures? Sony or IBM?

I do appreciate his honesty and not PR talk.

 

[_xxx_]

30-40% with logic redundancy is not bad at all. It's not like any chip of that size has much better yields. Athlons had less than 30% in the beginning and these are much less complex. The high-end gfx cards usually have less than 20% in the beginning as well AFAIK (though don't hang me for these numbers, it's just what I heard).

 

[RobertR1]

30-40% with logic redundancy is not bad at all. It's not like any chip of that size has much better yields. Athlons had less than 30% in the beginning and these are much less complex. The high-end gfx cards usually have less than 20% in the beginning as well AFAIK (though don't hang me for these numbers, it's just what I heard).

According to him the Cell is not using that so it's actually 10-20%. If Sony has to suck up the cost of "failed" chips, that's a lot of money, especially since unlike video cards and CPU cores these can't be turned into lesser sku's.

 

[PiNkY]

Cell should not be in initial ramp up, however. They originally planned to release their console months ago, while commercial products have been available at least since 2005. I highly doubt AMDs yields to be a less then 30% after speed binning (could you provide any link to that claim) as that would put them out of business fast.

 

[slider]

When it comes to absorbing costs - i.e. those Cell's with less than 7 working SPE's - depends how widely across Sony those "defective" Cell's can be spread. In part that depends on how well integrated Sony is under Stringer...

Maybe four SPE's for a Bravia would be overkill?

 

[Arty]

It looks like a minor slip up (or) brutally honest info. Either way I sense a statement coming up that will rubbish this one aside.

 

[Titanio]

This is old news, and already discussed, but..

According to him the Cell is not using that

He doesn't say that. He doesn't say it does, either - I'm not sure if it was ever confirmed if it does or doesn't (and no, I don't think 'logic redundancy' here refers to a disabled SPE, as he seems to be talking about more general redundancy as seen in memory).

The quoted figure would be yields on 8-SPE chips. If you only require 7, yields will be higher (how much, I don't know). If on top of that you had implemented logic redundancy across the chip, they'd be higher again.

 

[Arwin]

According to him the Cell is not using that so it's actually 10-20%. If Sony has to suck up the cost of "failed" chips, that's a lot of money, especially since unlike video cards and CPU cores these can't be turned into lesser sku's.

You're not reading that right. Mind the bit in italics:

"If you put logic redundancy on it, you can double that. It’s a great strategy, and I’m not sure anyone other than IBM is doing that with logic."

 

[Guden Oden]

According to him the Cell is not using that so it's actually 10-20%.

Do you have a quote where he actually says that?

Besides, the cells used in PS3 are only going to use 7 SPEs, not the full 8 (which is what the yield figure refers to). Hence, PS3-capable chip yield is going to be higher than the figures quoted, so please, drop the drama queen act, okay? "Yield hell" speculation is just a silly overdramatization.

 

[_xxx_]

You're not reading that right. Mind the bit in italics:

"If you put logic redundancy on it, you can double that. It’s a great strategy, and I’m not sure anyone other than IBM is doing that with logic."

Well the word is that ATI does it too with R580, though not confirmed either.

EDIT: does IBM produce the Cells for Sony at all? I thought it'll be produced in Sony/Toshiba plants?

 

[PiNkY]

Well logic redundancy in this case refers to the 'spare' spe. I think it's not too hard deducting that from the interview, as he explicitly mentions the 6spe cells and his statements about self-healing in the field. They have done the same thing in their mainframe cpus for decades.

 

[PiNkY]

ATI and NVIDIA have used the same approach for years. Damaged Quads can simply be disabled on their chips, which are then used in a cheaper sku...

 

[assen]

Maybe four SPE's for a Bravia would be overkill?

Is there a specific product announced for Cell besides the PS3? Something more than handwaving "you know, like TVs and such..."?

 

[_xxx_]

ATI and NVIDIA have used the same approach for years. Damaged Quads can simply be disabled on their chips, which are then used in a cheaper sku...

That's not what he meant, he meant the logic which is redundant within the unit (in a gfx-card that would be one pixel pipe, for Cell it would be one SPE for example), so you can get around the failure in a way that will prevent disabling units to get better yields.

 

[slider]

Is there a specific product announced for Cell besides the PS3? Something more than handwaving "you know, like TVs and such..."?

Specifically by Sony? And specifically CE you mean? Not as far as I know. I think Toshiba initially mentioned that "all their TV's" would have a Cell chip in them. But there was no further word on that.

If Sony are fabbing all their own chips their options would be:

a) Bin the <7SPE Cells.
b) Find something to do with them.

 

[PiNkY]

I am a bit lost as to what part of the interview you are referring. Logic redundancy mostly makes sense on larger units with well defined interfaces. First of all, the larger your die gets, the larger the probability of a defect. Now if you make everything redundant on a very fine grained scale your usable dies per unit of wafer area likely will go down and not up even though your yields improve. A pixel pipline in a GPU would make for a rather bad unit of redundancy because it shares its cu with other pipelines in its quad.

 

[Corwin_B]

50% of the die area of Cell is made of SPEs, right ? So if a chip has a single defect, there's a 50% chance it can still be used for the PS3 (and if it has several defects, there is a (much smaller) chance all the defects end in the same SPE area).

 

[Titanio]

Well logic redundancy in this case refers to the 'spare' spe. I think it's not too hard deducting that from the interview, as he explicitly mentions the 6spe cells and his statements about self-healing in the field.

I'm not sure given that he makes a comparison with memory redundancy, and explicitly putting extra bits into the chip. For Cell as a whole, the SPE isn't 'extra', Sony has just made it that way for PS3's. You could read it either way, but I don't think it's clear if he's referring to the a spare SPE there or lower-level redundancy.

 

[PiNkY]

I have never read or heard of a redundancy scheme for DRAMs that would not be based on spare rows or columns (or both), but then, I am no EE. Nevertheless, I find this quite interesting, so could you please point me to some of the fine grained redundancy schemes you allude to?

 

[Titanio]

I have never read or heard of a redundancy scheme for DRAMs that would not be based on spare rows or columns (or both), but then, I am no EE. Nevertheless, I find this quite interesting, so could you please point me to some of the fine grained redundancy schemes you allude to?

Beats me! My question is, what is he alluding to. I'm just not sure it's clear he's referring to disabled SPEs.

But in GPU land, I have seen the suggestion of redundant logic included at a lower level than dud quads. For example, in the shift from G70 to G71, the number of transistors dropped, and in some reviews I have seen this partially attributed to the removal of redundant logic within shaders.