Fully bindless architecture + all the FL 12_1 goodies + tier 3 conservative raster
Can't wait to try the 72 EU + EDRAM part.
I especially liked this:
Last edited:
Can't wait to try the 72 EU + EDRAM part.
I especially liked this:
Andrew, your link works just fine. Excellent deck, very excited about this level of featureset and performance in Skylake!
Does anyone know what the geometry throughput of Gen9 is? If I'm not mistaken Hawsell was one triangle/2clk? Is it the same for Broadwell and Skylake, or higher?
Alessio1989
Regular
This is the kinda GPU hardware feature support that I wish to see as soon as possible in a dedicated GPU lineup (with HBM2, standard swizzle and cross sharing node tier 3 : D ...yes, dream hardware to do dirty things with pointers and vram ).
Could Intel Gen9 iGPUs support HDR ASTC textures too?
What's the uncertainty regions precision of conservative rasterization, 1/256 or 1/512?
Could Intel Gen9 iGPUs support HDR ASTC textures too?
What's the uncertainty regions precision of conservative rasterization, 1/256 or 1/512?
That is really 4 per sub-slice right? Not that anyone gets a false idea for broxton
.Yes, 4 per sampler/subsliceThat is really 4 per sub-slice right? Not that anyone gets a false idea for broxton
Is there a listing for the tier levels for feature types like conservative rasterization?
Is the tier Gen 9 has based on having the ability to do things like inner and outer conservative raster, and the various other features that round out the functionality?
Is the tier Gen 9 has based on having the ability to do things like inner and outer conservative raster, and the various other features that round out the functionality?
pixelio
Newcomer
This page says that Tier 3 conservative rasterization (which Skylake has, right?) supports 1/512 uncertainty regions.
Hehe, yes and this is also what I remembered, since this was the first documented page about the differences.
Lookin now at the DX12 documentation it seems the requirements were downgraded:
https://msdn.microsoft.com/en-us/library/dn859368%28v=vs.85%29.aspx
Lookin now at the DX12 documentation it seems the requirements were downgraded:
https://msdn.microsoft.com/en-us/library/dn859368%28v=vs.85%29.aspx
pixelio
Newcomer
Yeah the page is out of date. It's actually something we will likely go in a slightly different direction on in terms of "tightening it up", as it turns out 1/512 (i.e. rounding) is not actually a sufficient condition to get pixel exact results between different implementations, which is really the ultimate goal. In practice any implementation that doesn't skip entire subpixels (i.e. 1/256) is equivalent until we can tighten a few other things, hence the Tier 3 requirements.
Yes, the main advantages being the inner coverage flag and the fact that it is truly conservative (does not cull post-snap degenerates).
Alessio1989
Regular
So what happen to those GPUs architecture planned to have a 1/512 pixel of uncertainty region? (if there were any). Sometimes MSDN is quite cryptic...
edit:
lol, looks like no-one wanted to fully up-to-date the SDK
Implementations are free to still have "narrower" regions where it can determine conclusively in a conservative manner, that's just not a sufficient condition for pixel exact results. Thus further tightening of the spec (via Tiers or otherwise) will likely have slightly different constraints than just the size of the uncertainty region. None of this is really a big deal until we can get to pixel-exact results between all implementations (arguably not super-important with CR anyways, but still a good goal)
On my i7-6700k HD 530 1.15 Ghz I get 99 fps (792 Mtri/s) in Cap Viewer HW Geometry Instancing, i5-4670 HD 4600 1.2 Ghz did 47 fps (376 Mtri/s).
Thanks, so it looks like throughtput has been doubled compared to gen7.5 and I would assume the theoretical peak is now at 1 tri/clk. I'm guessing that wouldn't scale up with additional slices? i.e. GT4e won't be pushing 3 tri/clk?
http://www.intel.com/content/www/us...ktop-6th-gen-core-family-datasheet-vol-1.html
There is a table on pages 36-37.
If I understand it correctly, there is an additional limit to Gen9 turbo frequency. The specified frequency (1.15GHz) can only be reached if no slices are active. If the slice is active, the maximum frequency is -1 or -2 bins, depending on SKU (I presume the bins are 50MHz?).
I wonder why that is.
There is a table on pages 36-37.
If I understand it correctly, there is an additional limit to Gen9 turbo frequency. The specified frequency (1.15GHz) can only be reached if no slices are active. If the slice is active, the maximum frequency is -1 or -2 bins, depending on SKU (I presume the bins are 50MHz?).
I wonder why that is.
And what is more interesting, if a second slice becomes active, the maximum frequency is lowered even more.
If it was just no slices active/any slices active, I would have imagined that the unslice needs less voltage to run at the maximum clock.
Similar threads
- Deleted member 7537
- PC Industry