IBM Cell Patent: Broadband Engine/PU Cache/Bus.

[j^aws]

DRAM as a whole is rather dense, especially the capacitor-less cell Toshiba's developed. It wouldn't allow another four PEs + 8 APUs. Maybe if it had been 64MB SRAM instead of eDRAM...

Thanks...How much more logic do you think it would allow instead in terms of PUs/ L2 cache, APUs/ SRAM?