Fewer syllables?
IBM announces 65nm Cell production
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Fewer syllables?
Cost reduction due smaller die size, less shielding, smaller costs for cooling solution, smaller power supply, etc.
See also:
http://www.beyond3d.com/content/news/87
http://www.beyond3d.com/content/articles/18/
i think thats advantage of 90nm over 65nm not "of 65nm over 90nm" is it???
i want to know what is better for 90nm
DuckThor Evil
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i think thats advantage of 90nm over 65nm not "of 65nm over 90nm" is it???
Well you get more silicon, as it is bigger, but I wouldn't start a party because of that.
edit:
Sorry, I read it wrong on assumption that you wouldn't ask because...well, 65nm is new and improved! If 90 nm was better, we wouldn't move to 65 nm! Benefits are basically nil, except as mmkay says, better yields to begin with. But as the manufacturing process matures, the small die size increases yields which improves cost effectiveness. And yields doesn't really mean anything if the net price is reduced. Would you rather have 85% efficiency and 150 chips per wafer, or 70% efficiency and 250 chips per wafer?i think thats advantage of 90nm over 65nm not "of 65nm over 90nm" is it???
cheers. don't know how go give reputation points though.
wouldn't increased wastage add to costs, though i feel yield outweighs waste by far anyway
Yes. A wafer costs something like $10,000. Onto that you print so many chips, and of those chips, so many will be faulty. The cost per chip is thus the cost of the wafer divided by the number of working chips. If you double the number of chips, you halve the price. If in doubling the number of chips the fault rate goes up enough to produce less working chips, the price increases. Generally that's not an issue, at least in the long run. I dunno how bad yields can get on a new process.wouldn't increased wastage add to costs, though i feel yield outweighs waste by far anyway
DuckThor Evil
Legend
No, if you have identical 12" wafers and you get 150 chips from 90nm and 250 chips with 65nm, by what logic would you rate the wastage as anything meaningful in this particular matter?
http://www.betanews.com/article/New_65nm_IBM_Cell_CPU_Promises_19_Power_Reduction/1173830474
19% of power reduction an they explain why they cannot use 65 nm CELL before:
19% of power reduction an they explain why they cannot use 65 nm CELL before:
well i don't understand fully but percentage of yield failure = percentage of wafer wasted
look at this rather stupid example
new manufacture with 900 chips @ 80% and each chip @ 10cm x 10cm
area as wastage = 900 x 0.2 x 10^2 = 18000cm^2 wastage
old manufacture with 100 chips @ 80% and each chip @ 30cm x 10cm
area as wastage = 100 x 0.2 x 30^2 = 18000cm^2 wastage, again same amount of material as wasted.
but you get larger quantity sold, larger profits. of course this assumes both process has equal % yield, which is different to 90nm vs 65nm i assume.
am i missing something here??? or did you said that increased waste does not add to costs???
Hmm... I don't know...
In the first case, you have 900 chips to sell. The second case, you only have 100 chips to sell. You make more money "at the same cost" (in your example).
Your maths is intrinsically hokey, because waste isn't the end product. The only concern is how many working chips you produce per wafer. This is a factor of size per die, and how many of those are broken. How much waste there is isn't counted. What's counted is how many working chips. They will look at reducing waste as that means more chips produced, but comparing different process nodes, all that matters is which puts out the most working chips per wafer (assuming running costs are the same - something I know nothing about!). Tryin to calculate wastage is back-to-front from calculating yields.
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