PC-Engine said:I don't think dc's cpu was that powerful.....(it did about 350 mips I believe)
SH-4@200MHz = 1.4 GFLOPS peak.
Raw transform ability is 10 million polys/sec.
Guden Oden said:Except, the Celeron in XB is 733MHz...
Guden Oden said:Actually it's not custom at all. It's a very standard celeron mobile CPU...
Raw transform is 10 million polys/sec? Isn't that within 20%(either way) of the ps2's cpu and the gamecube's cpu? I think a 500 mhz athlon could do around 15 million...
Vysez said:Here comes the specs
XCPU
Intel Custom
733MHz
32-bit INT
80-bit FP
64-bit MMX
128-bit SSE
32KB L1
128KB L2
1980 MIPS*
2.93 GFLOPS*
1.0 GB/sec Bus
DC CPU
Hitachi SH4
200MHz
32-bit INT
64-bit FP
24KB L1
360 MIPS*
1.4 GFLOPS*
800 MB/sec Bus
*Peaks
Simon F said:I don't recall the SH-4 having native double precision. Are you sure about that?
6.3.2 Floating-Point Unit Status/Control Register (FPSCR)
Floating-Point Unit Status/Control Register, FPSCR (32-bit, initial value = undefined)
31 22 21 20 19 18 17 12 11 7 6 2 10
Reserved FR SZ PR DN Cause Enable Flag RM
- FR: Floating-Point Register Bank
FR = 0: FPR0_BANK0?FPR15_BANK0 are assigned to FR0?FR15; FPR0_BANK1?
FPR15_BANK1 are assigned to XF0?XF15.
FR = 1: FPR0_BANK0?FPR15_BANK0 are assigned to XF0?XF15; FPR0_BANK1?
FPR15_BANK1 are assigned to FR0?FR15.
- SZ: Transfer Size Mode
SZ = 0: An FMOV instruction comprises a single-precision floating-point FMOV.
SZ = 1: An FMOV instruction comprises pair single-precision floating-point FMOVs (64
bits).
- PR: Precision Mode
PR = 0: Floating-point instructions are executed as single-precision operations.
PR = 1: Floating-point instructions are executed as double-precision operations (the operation of graphics-related instructions is undefined).
Do not set both SZ and PR to 1. This setting is reserved.
[SZ, PR] = 11: Reserved (FPU instruction operation is undefined.)
- DN: Denormalization Mode
DN = 0: A denormalized number is treated as a denormalized number.
DN = 1: A denormalized number is treated as zero.
- RM: Rounding Mode
RM = 00: Round to Nearest
RM = 01: Round to Zero
RM = 10: Reserved
RM = 11: Reserved
Notes:
1. The SZ and PR bits and cause, enable, and flag fields for exceptions O/U/I have been added.
2. The cause field for exception E has been added.
SZ = 1: An FMOV instruction comprises pair single-precision floating-point FMOVs (64 bits).
· Instruction execution time
- Latency (FMAC/FADD/FSUB/FMUL): 3 cycles (single), 8 cycles (double)
- Pitch (FMAC/FADD/FSUB/FMUL): 1 cycle (single), 6 cycles (double)
- Note: FMAC is supported for only single precision.
· 3D graphic instructions:
- 4-dimentional vector transformation and matrix operation (FTRV), 4 cycles (pitch), 7 cycles (latency)
- Inner product of 4-dimentional vectors (FIPR), 1cycle (pitch), 4 cycles (latency)