How powerful was the Dreamcast?

Seriously, lets settle this now, how powerful was the Dreamcast?

  • Around Voodoo 2

    Votes: 0 0.0%
  • Banshee!

    Votes: 0 0.0%
  • Geforce 2!(come on, seriously, you're saying DC beats kyro 2?)

    Votes: 0 0.0%
  • Geforce 2 Ultra

    Votes: 0 0.0%
  • Geforce 3

    Votes: 0 0.0%
  • GeforceFX 5200 Ultra(trick answer, this one is back at the geforce 2 level!)

    Votes: 0 0.0%

  • Total voters
    43
PC-Engine said:
I don't think dc's cpu was that powerful.....(it did about 350 mips I believe)

SH-4@200MHz = 1.4 GFLOPS peak.

Raw transform ability is 10 million polys/sec.

Raw transform is 10 million polys/sec? Isn't that within 20%(either way) of the ps2's cpu and the gamecube's cpu? I think a 500 mhz athlon could do around 15 million...

BTW, a 600mhz celeron would do 1620 MIPS, and 804 MFLOPS, so could the dreamcast cpu be in some ways more powerful than the xbox's?
 
Guden Oden said:
Except, the Celeron in XB is 733MHz... :)

It was the closest I could find, the xbox's main memory has worse latency than a pc would have had, and the SH-4's specs would still have it with higher MFLOPS.
 
OTOH, the Celly has higher bus bandwidth (is SH4 32 or 64 bit bus?), certainly much higher memory bandwidth, it actually has a L2 cache too (and a fast one I might add), and so on. I'd say that SH4 is overall pretty outclassed on all fronts, which isn't surprising really.

It may well be a very efficient design, but it's not in the same league.
 
Here comes the specs :D

XCPU
Intel Custom
733MHz
32-bit INT
80-bit FP
64-bit MMX
128-bit SSE
32KB L1
128KB L2
1980 MIPS*
2.93 GFLOPS*
1.0 GB/sec Bus

DC CPU
Hitachi SH4
200MHz
32-bit INT
64-bit FP
24KB L1
360 MIPS*
1.4 GFLOPS*
800 MB/sec Bus

*Peaks
 
Guden Oden said:
Actually it's not custom at all. It's a very standard celeron mobile CPU...

Since i don't remember exactly the "differences" between a celeron and the Xcpu, i won't discuss it, but i remember that the Xcpu had a few thing that a Celeron didn't have...
Btw you're talking about a Mobile Celeron , so maybe it has those "differences" and then you are right. :D
 
The differences between a normal Coppermine Celly and the one in the X-Box is that the Coppermine Celly has a 66 MHZ bus rather than a 133 MHZ bus and it has an eight way asocshiated(Sorry for the horrible spelling of that word.) cache rather than a four way one. Apparently the mobile Cellys at the time were made just like that.
 
Raw transform is 10 million polys/sec? Isn't that within 20%(either way) of the ps2's cpu and the gamecube's cpu? I think a 500 mhz athlon could do around 15 million...

Yes according to Hitachi raw transform is 10 million. The EE in PS2 has raw transform of 66 million.
 
Vysez said:
Here comes the specs :D

XCPU
Intel Custom
733MHz
32-bit INT
80-bit FP
64-bit MMX
128-bit SSE
32KB L1
128KB L2
1980 MIPS*
2.93 GFLOPS*
1.0 GB/sec Bus

DC CPU
Hitachi SH4
200MHz
32-bit INT
64-bit FP
24KB L1
360 MIPS*
1.4 GFLOPS*
800 MB/sec Bus

*Peaks

mind you, sh4's fpu was anything but your regular fp unit - it has SIMD (4-way over single-precision) and matrix ops. for comparison, amd's 3dn (not 3dn+) is plain 2-way (single-prec) w/o any matrix ops (though i personally like the sucker)

ed: to sum it up, sh4's fpu is capable of: 64bit (double-prec), single-prec SIMD (4x) and single-prec matrix (4x4) ops
 
I don't recall the SH-4 having native double precision. Are you sure about that?
 
Simon F said:
I don't recall the SH-4 having native double precision. Are you sure about that?

according to this sh4 progman i've got here:
Code:
6.3.2 Floating-Point Unit Status/Control Register (FPSCR)

Floating-Point Unit Status/Control Register, FPSCR (32-bit, initial value = undefined)
31    22 21 20 19 18 17 12 11   7 6  2 10
Reserved FR SZ PR DN Cause Enable Flag RM

-  FR: Floating-Point Register Bank
FR = 0: FPR0_BANK0?FPR15_BANK0 are assigned to FR0?FR15; FPR0_BANK1?
FPR15_BANK1 are assigned to XF0?XF15.
FR = 1: FPR0_BANK0?FPR15_BANK0 are assigned to XF0?XF15; FPR0_BANK1?
FPR15_BANK1 are assigned to FR0?FR15.
-  SZ: Transfer Size Mode
SZ = 0: An FMOV instruction comprises a single-precision floating-point FMOV.
SZ = 1: An FMOV instruction comprises pair single-precision floating-point FMOVs (64
bits).
-  PR: Precision Mode
PR = 0: Floating-point instructions are executed as single-precision operations.
PR = 1: Floating-point instructions are executed as double-precision operations (the operation of graphics-related instructions is undefined).
Do not set both SZ and PR to 1. This setting is reserved.
[SZ, PR] = 11: Reserved (FPU instruction operation is undefined.)
-  DN: Denormalization Mode
DN = 0: A denormalized number is treated as a denormalized number.
DN = 1: A denormalized number is treated as zero.
- RM: Rounding Mode
RM = 00: Round to Nearest
RM = 01: Round to Zero
RM = 10: Reserved
RM = 11: Reserved
Notes:
1. The SZ and PR bits and cause, enable, and flag fields for exceptions O/U/I have been added.
2. The cause field for exception E has been added.

alas the revision notes raise a question as to when actually was double precision introduced
 
I think that...
Code:
SZ = 1: An FMOV instruction comprises pair single-precision floating-point FMOVs (64 bits).
...was supported (handy for loading vectors rapidly), but I believe that double precision was probably deemed to be overkill and I would tend to agree.
 
well, for what it's worth

Code:
·  Instruction execution time
-  Latency (FMAC/FADD/FSUB/FMUL): 3 cycles (single), 8 cycles (double)
-  Pitch (FMAC/FADD/FSUB/FMUL): 1 cycle (single), 6 cycles (double)
-  Note: FMAC is supported for only single precision.
·  3D graphic instructions:
-  4-dimentional vector transformation and matrix operation (FTRV), 4 cycles (pitch), 7 cycles (latency)
-  Inner product of 4-dimentional vectors (FIPR), 1cycle (pitch), 4 cycles (latency)
 
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