HotChips 17 - More info upcoming on CELL & PS3

[PC-Engine]

But you can't know that from speculation, even manufacturer themself wouldn't know without trial.

Obviously, but I'm assuming IBM is compentent and has the fab technology required to design a 4 core version without needing a 5th redundant core. All the incredients are there and you have a good gorrmet chef doing the cooking.

 

[Shifty Geezer]

When you have a huge chip that takes up over 220 sq mm of space that has 8 small cores, then it's obvious you might have problems with one of those cores. With 4 big cores that take up less than 200 sq mm, there's no need for redundant cores.

Why does 220 mm^2 have a fair chance of an error that incapacitates a core, whereas a 200 mm^2 die not have the same percentage chance of failure (less 10% for 10% less area)?

If we assume the chance of a knackered SPE is high enough to warrant a redundant core by design there must be quite a large chance of a fault in that 220 mm^2, which suggests the same liklihood a 4 core XCPU would take a hit. If the risks of faults weren't that high, and the majority of 220 mm^2 dies could be produced without fault, we'd be seeing 8 SPE Cells in use.

Note : I know nothing about what current yields are like, hence why I ask.

 

[Guden Oden]

Stop pointing out the obvious as if it actually means something with respect to a 4 core CPU. Keep on thinking 1MB L2 is the Holy Grail for 3 cores while magically becoming a deathbead for 4. You don't have a clue what you're talking about dude.

I never said 1MB was a holy grail, that's just your fanb0y mind making things up as usual. What I am saying (and this is the truth) that 1MB shared amongst 8 threads is going to be harder to use efficiently than 1MB shared amongst 6. (And 6 is already quite a lot, considering PC processors typically use 1MB on just ONE, or at most, two.)

So go take your hostility someplace else alright?

 

[PC-Engine]

I never said 1MB was a holy grail, that's just your fanb0y mind making things up as usual. What I am saying (and this is the truth) that 1MB shared amongst 8 threads is going to be harder to use efficiently than 1MB shared amongst 6. (And 6 is already quite a lot, considering PC processors typically use 1MB on just ONE, or at most, two.)

So go take your hostility someplace else alright?

Strawman argument...;-)

Why does 220 mm^2 have a fair chance of an error that incapacitates a core, whereas a 200 mm^2 die not have the same percentage chance of failure (less 10% for 10% less area)?

Two reasons:

1. CELL is at 220+ sq mm which is larger than 200 sq mm.
2. CELL is also comprised of 8 cores.

Fewer cores and a smaller die means fewer chances of a core being bad.

 

[Shifty Geezer]

Any minute now Vysez is going to appear in a puff of logic and start complaining. Time to 'duck and cover'.

 

[Phil]

Two reasons:

1. CELL is at 220+ sq mm which is larger than 200 sq mm.
2. CELL is also comprised of 8 cores.

Fewer cores and a smaller die means fewer chances of a core being bad.

8 SPEs and 1 PPE, so I count 9 cores. Loosing 1 SPE for yields is less expensive than loosing an entire PPE on Xenon due to yields (which is why we have 7 SPEs in PS3). Chances are that the 4th core you're dreaming about would be lost due to yields anyway, so you still end up with 3 regardless.

Then in addition comes heat - and there's a good chance that the PPE generates quite a bit more heat than the SPEs on CELL - which adds to the point that a 4th PPE on Xenon would bring heat up even more per mm^2.

 

[PC-Engine]

Chances are that the 4th core you're dreaming about would be lost due to yields anyway, so you still end up with 3 regardless.

Chances are? Says who? If you lose a core then you don't use the chip. At less than 200 sq mm and with only 4 cores you won't have too many dies with dead cores. You act like IBM absolutely couldn't fit another core and completely ignore the fact they have cost and power goals. Doesn't mean a 4 core version consuming more power isn't feasible.

Then in addition comes heat - and there's a good chance that the PPE generates quite a bit more heat than the SPEs on CELL - which adds to the point that a 4th PPE on Xenon would bring heat up even more per mm^2.

Of course the power consumption would go up, but thanks for pointing out the obvious. If you had read the previous posts, my calculations indicate the power consumption would be around 108W around the same as a 3.2GHz Prescott. Last time I checked the Prescott didn't need any special water cooling. In fact TDP of P4 3.8GHz is 115W.

 

[Phil]

Chances are? Says who? If you lose a core then you don't use the chip. At less than 200 sq mm and with only 4 cores you won't have too many dies with dead cores. You act like IBM absolutely couldn't fit another core and completely ignore the fact they have cost and power goals. Doesn't mean a 4 core version consuming more power isn't feasible.

CELL in PS3 using 1 SPE less to improve yields says so. If you have the same failure ratio that is reason enough for STI to disable one small SPE, you'd be loosing an entire PPE on Xenon in a lot of cases - and that costs money AND is a waste of silicon. It's either that and you get one hell of an expensive 4-core design (with the same amount of cache) or you save the buck and go with something more efficient, easier and cheaper = 3 cores.

In fact, I'm not even sure why I'm bothering. Obviously, it isn't feasible in reality or else they would have done it. It's a non-issue, end of discussion.

 

[PC-Engine]

In fact, I'm not even sure why I'm bothering. Obviously, it isn't feasible in reality or else they would have done it.

Riiiight...because die size and cost isn't a factor for what MS wants.

 

[Shifty Geezer]

PC-Engine : If your so sure there won't be an issue with duffed cores on a 4 core XCPU, please answer my first query on the matter with some useful information as to why...

Why does 220 mm^2 have a fair chance of an error that incapacitates a core, whereas a 200 mm^2 die not have the same percentage chance of failure (less 10% for 10% less area)?

If we assume the chance of a knackered SPE is high enough to warrant a redundant core by design there must be quite a large chance of a fault in that 220 mm^2, which suggests the same liklihood a 4 core XCPU would take a hit. If the risks of faults weren't that high, and the majority of 220 mm^2 dies could be produced without fault, we'd be seeing 8 SPE Cells in use.

 

[PC-Engine]

PC-Engine : If your so sure there won't be an issue with duffed cores on a 4 core XCPU, please answer my first query on the matter with some useful information as to why...

The more cores on a die, the higher the chances of a core being bad. 8 is two times 4. If you tak out the SPEs and replaced them with 3 PPEs you would get better yields and would not need a 5th PPE for redundancy.

 

[rendezvous]

The more cores on a die, the higher the chances of a core being bad. 8 is two times 4. If you tak out the SPEs and replaced them with 3 PPEs you would get better yields and would not need a 5th PPE for redundancy.

That is assuming that a smaller core has as high risk of ending up bad as a larger core, which generally isn't true.

 

[PC-Engine]

That is assuming that a smaller core has as high risk of ending up bad as a larger core, which generally isn't true.

The size of the cores being talked about here is irrelevant since they're within the limits of standard core designs. If the cores in the XCPU is more likely to fail then why doesn't IBM put in a 4 th core for redundancy? If CELL had 2 SPEs and 2 PPEs, would they need to put in a 3rd SPE for redundacy? I think not.

 

[Guden Oden]

Strawman argument...;-)

No, of course not, that's a silly thing to say.

Maybe you should look up the definition of a strawman, because you don't seem to have a clear grasp of what it actually means, considering:

Two reasons:

1. CELL is at 220+ sq mm which is larger than 200 sq mm.
2. CELL is also comprised of 8 cores.

Fewer cores and a smaller die means fewer chances of a core being bad.

...That I wasn't talking about cell, or sony or anything regarding such.

In accusing me of strawman argumentation, you yourself set up a perfect example of a strawman. It's so rediculous you should be laughed straight out of town.

I might ask what the cache of xcpu has to do with the die size of cell, but I'd only get a trolling gibberish response from you as usual. Time to go take your lithium, your anti-sony hate is exploding to new levels of incoherence...

 

[PC-Engine]

No, of course not, that's a silly thing to say.

Maybe you should look up the definition of a strawman, because you don't seem to have a clear grasp of what it actually means,

What does 4 cores sharing 1MB of L2 have anything to do with getting a less performing CPU? That's right nothing...nada..zilch. Where is this fantasy drop in performance of a 4 core CPU? Why even bring PC CPUs and 2MB caches into this discussion? According to your logic every CPU needs at least 1MB of cache?

That I wasn't talking about cell, or sony or anything regarding such.

Why are you responding to something that has NOTHING to do with YOU?

In accusing me of strawman argumentation, you yourself set up a perfect example of a strawman. It's so rediculous you should be laughed straight out of town.

I might ask what the cache of xcpu has to do with the die size of cell, but I'd only get a trolling gibberish response from you as usual. Time to go take your lithium, your anti-sony hate is exploding to new levels of incoherence...

Strawman arguments are the kind that have nothing to do with what people are actually talking about. Nobody said 4 cores sharing 1MB of L2 would be easier for programmers to utilize. You and Mr. Scarecrow can spend all day arguing about 8 threads sharing the 1MB of L2 Holy Grail. I coudn't care less.

 

[MrFloopy]

The more cores on a die, the higher the chances of a core being bad. 8 is two times 4. If you tak out the SPEs and replaced them with 3 PPEs you would get better yields and would not need a 5th PPE for redundancy

In the last few days I have seen some of the silliest arguments on this board (mostly to do with the necessity of a HDD and the horrors of split skus ), however this takes the cake.

So what your saying is that optical and material deficiencies are aware of sub division of functional units. So titanics problem was that they had too many self containing water tight sections, not that the iceberg tore through too large a proportion of the boat?

 

[Farid]

Chillax!

The discussion is starting to be way too heated. Time to relax, folks.

And Shifty, I'm never complaining! I'm a hater, not a whiner!

 

[Carl B]

PC-Engine, the problem here is you think the more cores, the higher the chances of a defect - when in fact it's simply the larger the die, the higher the odds of a defect being on die. Since Cell has a large area of which the majority is composed of the SPE's, it's easy to say 'let's just take one of these out of the official spec anyway,' and watch as your yields jump up as your dies are now able to withstand a defect on the majority of chips (assumign it doesn't land across two SPEs, or the PPE, etc..)

On Microsoft's side, were they to go to a four-core design they would be increasing the die size, thus increasing the chances of a defect on die. And of course with this design, the entire chip would need to be tossed. More dies with defects + larger dies = less functional chips + higher cost per chip.

I'm sure Microsoft could have gone with a four core design, but they didn't. We can't guess the reasons, but I imagine cost, heat, and yields all play a roll.

 

[_phil_]

CELL in PS3 using 1 SPE less to improve yields says so.

Could we have a dev with actual devkits confirm that ?

 

[dskneo]

In the last few days I have seen some of the silliest arguments on this board (mostly to do with the necessity of a HDD and the horrors of split skus ), however this takes the cake.

So what your saying is that optical and material deficiencies are aware of sub division of functional units. So titanics problem was that they had too many self containing water tight sections, not that the iceberg tore through too large a proportion of the boat?

touché

Like the quote says, Defects are counted per mm'2 and not per core.
having 9 Cores in 250mm'2 saves alot more money than having 3 cores in 200mm'2.
And thats it. No more science in here.

Defects are gonna hit the 200mm'2.
-What matters is that, if it hits a small space of the 3 Core CPu, 1/3 of the cpu goes to garbage because one tiny defect on one core disables the FULL core. 2 cores remain.

-If it hits the same small space of the 9 Core CPu, 1/8 of the Cpu goes to garbage, because the tiny defect is gonna hit a smaller division (smaller core) and that saves the others from being dragged into garbage. 8 Cores remain.

what pc-engine thinks is that the defects ARE HUGE, enormous, so by his logic a 3 core CPU is gonna put one full core to garbage anyway, while in the 9 Core cpu many many cores go to garbage.
But defects are not HUGE... are tiny!

Fewer cores and a smaller die means fewer chances of a core being bad.

wrong.
defects happen per space of die. Its correct that Smaller the Die is fewer chances of damage.
But Fewer the cores means BIGGER Cores to fill the sapce. and the Bigger the cores are, bigger the waste if a tiny defect hits that die space.