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- Thread starter ninelven
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Re: Rough outline of PS3/X360 arch.
Yep, that's how I see it. Apart from the Xenos-EDRAM effective 256 GB/s interconnect.
Daves going to clear that up...but I still see that as 32 GB/s write, 16 GB/s read for now...
ninelven said:I made a couple of outlines in paint for the systems. Just wanted to post them to make sure I was understanding correctly.
Is this more or less correct?
Yep, that's how I see it. Apart from the Xenos-EDRAM effective 256 GB/s interconnect.
Daves going to clear that up...but I still see that as 32 GB/s write, 16 GB/s read for now...
Re: Rough outline of PS3/X360 arch.
Nice job ninelven.
You may want to clarify that on the Xbox 360 eDRAM that there is logic on it. It seems, at this point, that the 256GB/s is between the logic ON the eDRAM and the eDRAM, and that the bandwidth between the GPU and the eDRAM is 256GB/s *effective* which is something like 32GB/s write and 16GB/s read as Jaws said. But we have no firm info or clarification :?
As for what the benefit of eDRAM, it takes some of the load off the UMA by isolating the frame buffer. So hypothetically if your framebuffer uses 10GB/s, instead of that eating away at your 23GB/s UMA you have isolated that. Like Jaws mentioned yields and also from HardOCP:
http://www.hardocp.com/article.html?art=NzcxLDM=
Another thing is it uses DRAM and not SRAM or 1T-SRAM. That makes it cheaper and smaller (at least according to Anandtech, so take that with a grain of salt).
Nice job ninelven.
You may want to clarify that on the Xbox 360 eDRAM that there is logic on it. It seems, at this point, that the 256GB/s is between the logic ON the eDRAM and the eDRAM, and that the bandwidth between the GPU and the eDRAM is 256GB/s *effective* which is something like 32GB/s write and 16GB/s read as Jaws said. But we have no firm info or clarification :?
As for what the benefit of eDRAM, it takes some of the load off the UMA by isolating the frame buffer. So hypothetically if your framebuffer uses 10GB/s, instead of that eating away at your 23GB/s UMA you have isolated that. Like Jaws mentioned yields and also from HardOCP:
http://www.hardocp.com/article.html?art=NzcxLDM=
Another thing is it uses DRAM and not SRAM or 1T-SRAM. That makes it cheaper and smaller (at least according to Anandtech, so take that with a grain of salt).
Ken Ktuaragi from his recent interview...
Cell can access RAM transparently. Is that through RSX then, or has it got it's own lines to the DDR? What's said implies that Cell can access DDR without interfering with RSX's bandwidth on the matter. Or is it really a case of data being passed from RSX to Cell on request?
