Current Generation Hardware Speculation with a Technical Spin [post GDC 2020] [XBSX, PS5]

[Deleted member 13524]

It can't be, considering BVH is 1 GB to 1.5 GB and IC is only 128 Meg.

Surely the BVH calculations can be split among lower amounts of memory than those monolithic 1.5GB. That's probably how much the whole scene takes from BVH on one frame, but the 128MB cache can be filled and flushed several times throughout the course of building one frame.

 

[RDGoodla]

The 32MB L3 on Zen 2 CPUs takes up roughly half of the 75mm^2 chiplet, so ~50mm^2 for 64MB really is a lower bound estimate here.

Also if you can’t be bothered to do your own research, please at least be polite to other members.

How many infinity cache is useful? Can 32MB be the lower bound if we want to increase memory efficiency by 30%?

 

[scently]

I think this is really simple. It seems to me Sony branched development of its own GPU hardware, based on RDNA2, before the full features of RDNA2 was fully developed. For my money, I'd guess that Mesh Shader, VRS (at least the version used by MS and AMD), and SF are probably not in the PS5 version GPU. Does this mean the PS5 GPU is not based on RDNA2? No. The PS5 GPU is still based on RDNA2 because at the very least, it has RT hardware in the GPU which requires a modification of the Texture sampling block. This is by far the most fundamental differentiator between RDNA1 and RDNA2. All the other features can be emulated in software (VRS was used in COD:MW 2019 on consoles), have and adjacent implementation (Geometry Engine (although I think this was already available on AMD hardware going back to Vega card), and might not be needed going by Sony's faster IO block/SSD (SF). So it's not a full-fledged RDNA 2 part.

The extent to which these other features will show or present significant performance benefits over their exclusion vs what is present in the PS5 setup, I guess we will have to wait and see. For the most part, these features are not transparent or obvious to the end-user except by seeing maybe a res or framerate difference between the two consoles and maybe a developer interview by DF maybe, telling us that this is as a result of utilizing so, so, and so features as an example.

 

[Kugai Calo]

How many infinity cache is useful? Can 32MB be the lower bound if we want to increase memory efficiency by 30%?

We would need to profile some games to really know!

 

[eastmen]

I think this is really simple. It seems to me Sony branched development of its own GPU hardware, based on RDNA2, before the full features of RDNA2 was fully developed. For my money, I'd guess that Mesh Shader, VRS (at least the version used by MS and AMD), and SF are probably not in the PS5 version GPU. Does this mean the PS5 GPU is not based on RDNA2? No. The PS5 GPU is still based on RDNA2 because at the very least, it has RT hardware in the GPU which requires a modification of the Texture sampling block. This is by far the most fundamental differentiator between RDNA1 and RDNA2. All the other features can be emulated in software (VRS was used in COD:MW 2019 on consoles), have and adjacent implementation (Geometry Engine (although I think this was already available on AMD hardware going back to Vega card), and might not be needed going by Sony's faster IO block/SSD (SF). So it's not a full-fledged RDNA 2 part.

The extent to which these other features will show or present significant performance benefits over their exclusion vs what is present in the PS5 setup, I guess we will have to wait and see. For the most part, these features are not transparent or obvious to the end-user except by seeing maybe a res or framerate difference between the two consoles and maybe a developer interview by DF maybe, telling us that this is as a result of utilizing so, so, and so features as an example.

We can play the speculation game all day long imo. I dont' think we will ever know unless amd or sony come out and say what it is.

For all we know AMD's 2019 flaghship that was canceled could have had an RT implementation that didn't have vrs and other features and the ps5 is a hybrid of this and navi 2 .

Or it could have a bunch of stuff that is in navi 3 and is still a hybrid navi 2 .

My only question is if XSeries , PS5 and Navi 2 pc were all being designed around a similar time frame why would Sony get Navi 3 features in navi 2 while amd left them out of the desktop product they had coming out at the same time ?

 

[Allandor]

Well, they mentions this in their presentation. There was always a hint at "patented solutions". So Sony can't use those in their GPUs.
There was a rumor that Sony has their own RT implementation and this would really explain it. Might be better or worse.

 

[scently]

We can play the speculation game all day long imo. I dont' think we will ever know unless amd or sony come out and say what it is.

For all we know AMD's 2019 flaghship that was canceled could have had an RT implementation that didn't have vrs and other features and the ps5 is a hybrid of this and navi 2 .

Or it could have a bunch of stuff that is in navi 3 and is still a hybrid navi 2 .

My only question is if XSeries , PS5 and Navi 2 pc were all being designed around a similar time frame why would Sony get Navi 3 features in navi 2 while amd left them out of the desktop product they had coming out at the same time ?

Which RDNA3 feature does PS5 have? I don't think I have seen or heard of a single feature present in the PS5 that could be construed as a feature from RDNA3 which we know nothing about.

 

[eastmen]

Which RDNA3 feature does PS5 have? I don't think I have seen or heard of a single feature present in the PS5 that could be construed as a feature from RDNA3 which we know nothing about.

Its a rumor that has been spread as extra sauce. People have spread it and talked about it for a very long time. I think they point to the geometry engine and that it was a custom gpu

 

[iroboto]

On your claims over what I'm thinking.
I never mentioned 128MB. Why would a 36CU GPU have the same cache amount as a 80CU GPU? 128MB and its die area on the PS5 is something you fabricated by yourself, please refrain from putting words in my mouth.

Fair enough, that's on me. I apologize.

I'm totally aligned with wanting PS5 to have infinity cache. Realistically _any_ sort of massive cache would be great for all chips and silicon. But especially for PS5 of which, having the same number of CUs as 4Pro, more than doubling it's computational power via clockrate. That means every single cycle on the PS5 really matters and running at such a high clockrate means memory stalls are going to affect it badly, tossing away all of those cycles. I get it fully and I'm fully on board with it having as much cache as possible.

But I think for clarity sake, we can't just call any amount of cache infinity cache. If Sony comes out and says they have it, they have it. Otherwise, its not. There could be a large volume of cache on the PS5, just like on XSX thye have 76MB on chip total, but no platform holder has come out to say that they've got infinity cache on their processor.

There's 2 ways to look at this really.
1) you need tons of bandwidth to feed a lot of CUs.
2) if you have super high clock rate, you want to a large amount of cache to keep that as fed as possible.

The two don't necessarily have to be a joined requirement, you can have large storage without high bandwidth. And you can low storage and high bandwidth.

So I don't want to be twisting Cerny's words on cache, to represent infinity cache. To me, I think PS5 having a lot of cache is going to be more critical for it's performance than having high bandwidth.
While for XSX, having a low amount of cache with higher bandwidth would be better to feeding more CUs at once. And in the case of 6900XT, you need both.

I don't know what infinity cache does, but it doesn't sound like L3

I think if we're going to set ground rules on determining if these consoles have infinity cache, we need them to explicitly say it.
Having cache outside of l2 is just not sufficient.

 

[function]

It can't be, considering BVH is 1 GB to 1.5 GB and IC is only 128 Meg.

Perhaps they mean that the total uplift to effective BW is essential is getting the RT performance they want out of a relatively meagre 256-bit bus? I guess that anything you could save on other areas of rendering is going to free up more BW for a large BVH tree...

 

[PSman1700]

This is going to be an interesting week.

https://twitter.com/x/status/1321501744623357952

Always thought the idea that xbox is true/full rdna2 and ps5 isnt (rdna1.5?) was some kind of fud).
But well here we are. It probably wont matter outside of paper specs. Or sony has their own exotic solutions? Intresting atleast.

 

[scently]

This is an interesting question. I don't know enough about this even in general, but thinking about it, I suppose if you are indeed treating it like it's in vram (which has been mentioned a few times) your IO unit would pass the data to whatever requested it, in as similar a manner as possible to how vram is accessed. So maybe you evict something from some level of cache and dump it there. For textures I suppose L1 would make most sense?

Those "SoC memory coherency" things on the die shot seem kind of beefy, and there seems to be one per shader engine. I'll point my finger at them and say based on nothing in particular that they manage the job.

I suppose you'd have to be able to chose whether data was copied in vram afterwards, or simply used and discarded to be fetched again if needed.

I have been wondering what those things are. There wasn't any explanation of what they are or what they do in the HotChips presentation and yet they occupy a bit of space on the XSX SoC.

 

[Deleted member 13524]

But I think for clarity sake, we can't just call any amount of cache infinity cache.

Yes, I did mention "similar implementation".
Though I don't think the term will be limited by amount alone.
When RGT leaked the Infinity Cache for the first time, they said AMD went this way instead of wider GDDR or HBM because this implementation would allow it to provide higher performance on the PC APUs that are stuck with 128bit DDRx or LPDDRx.
So if we see e.g. a Van Gogh with say 16 CUs, we could be looking at significantly lower amounts of iGPU LLC, (25.6MB if we were to scale down Navi 21's LLC), and AMD would probably call it Infinity Cache still.


By the way, I don't think it's very accurate to assume 1MB of LLC on RDNA2 is taking as much die area as 1MB of L3 on Zen2.
The first one must work at up to 4.6GHz, whereas the second only goes up to half of that, meaning more density-optimized transistors can be used.

It sure doesn't look like the Infinity Cache in Navi 21 is taking up 128mm^2, unless that chip is 600mm^2 big.

 

[function]

Always thought the idea that xbox is true/full rdna2 and ps5 isnt (rdna1.5?) was some kind of fud).
But well here we are. It probably wont matter outside of paper specs. Or sony has their own exotic solutions? Intresting atleast.

GPUs have lots of components and many are worked on in parallel, with some features being ready before others. For a customer looking for a semi-custom part, it means you can end up with a GPU that has elements of the last PC part and some of the upcoming PC part. This could well be the case for PS5.

It's also true that a semi-custom customers' requirements can influence elements of upcoming designs. Indeed, Cerny indicated that we should look for a similar product arriving at the same time to show the fruit of some of their collaborations - so RDNA 2.

 

[BRiT]

It sure doesn't look like the Infinity Cache in Navi 21 is taking up 128mm^2, unless that chip is 600mm^2 big.

Some estimates were a little over 100mm^2 in the AMD thread. Not sure if entirely accurate.

 

[Johnny Awesome]

As I've been saying for weeks: There's no secret sauce. If MS and Sony aren't talking about a feature, their machines don't have it.

 

[iceberg187]

https://twitter.com/x/status/1321555899811565568

Tommy McClain

In reading about this, it seems to mean that since Microsoft was very intertwined with some of the development that they simply waited until the feature set was full?

This appears to give credence to why Sony had dev kits out early, compared to Microsoft.

 

[SmooTh]

Tom Warren
"All I know is that Sony picked a particular part, and Microsoft waited for reasons I'll explain soon."

 

[iceberg187]

Tom Warren
"All I know is that Sony picked a particular part, and Microsoft waited for reasons I'll explain soon."

Is this on Twitter? If so, I can't see that. Please link us. Thanks.

 

[Inuhanyou]

Tom Warren
"All I know is that Sony picked a particular part, and Microsoft waited for reasons I'll explain soon."

These companies pick out "parts" instead of assembling different customized ingredients together to achieve a desired APU?

It sounds like this guy is saying sony picked out a 5700xt, added their own features and boosted the clock frequency while ms waited for the 6000 series. But thats silly.

Both of these machines are using variations of rdna2 customized to their needs. Id say this kind of thing is only used in ammunition fights between warriors.