I wonder if one scenario for memory access for a given clock cycle could be something like:Ah, that makes a lot more sense! I did wonder, but the way it was phrased (two pools with separate BW, like PS3's split RAM) caught me off guard. Should pay more attention.
4x2x16-bit + 6x1x16-bit for GPU or CPU, respectively.
6x1x16-bit for CPU or GPU, respectively (to the higher addresses from 1-2Gbyte)
i.e. 224-bit access + 96-bit access in a given cycle, if that makes sense for simultaneous CPU/GPU no contention? Remember that GDDR6 operates a 32-bit DRAM with twin 16-bit channels, so I'm saying that on the 6x2GB DRAMs, half of the chans are either GPU or CPU with the 1GB DRAMs being given over to either the CPU or GPU.
224/320 = 14/20 = 392 GB/s
96/320 = 6/20 = 168GB/s
That's assuming the CPU hits all 6 DRAMs simultaneously, although I guess it depends if the OS is spread out across 3 DRAMs (1GB + 1GB + 0.5GB) or if it is spread out on all 6 DRAMs to maximize CPU OS bandwidth for some ducky reason.
I don't know if any of that really matters.
Code:
[1GB] [1GB] [1GB] [1GB]
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[x16][x16] [x16][x16] [x16][x16] [x16][x16]
[1+1 GB] [1+1 GB] [1+1 GB] [1+1 GB] [1+1 GB] [1+1 GB]
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[x16][x16] [x16][x16] [x16][x16] [x16][x16] [x16][x16] [x16][x16]
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