Broadway specs

[Entropy]

Because PowerPC 750CL has a size of 16mm^2 and Broadway size is 25mm^2, just the the half than the PowerPC 750GX at 130nm.

That 25mm^2 number was estimated from how many dies IBM squeezed onto a 300mm wafer. All it takes is a 0.5 mm margin per side and CPU to the neighbouring dies on the wafer and we have a 4x4 die instead of a 5x5 one. Since we know there are going to be margins for cutting the dies, this seems quite reasonable, no?

I can't help feeling that going with a SoC would have made some sense given the tiny die sizes. I definitely can't see Nintendo shrinking the CPU to 45nm geometries at the end of the console life cycle!

 

[Shifty Geezer]

That 25mm^2 number was estimated from how many dies IBM squeezed onto a 300mm wafer. All it takes is a 0.5 mm margin per side and CPU to the neighbouring dies on the wafer and we have a 4x4 die instead of a 5x5 one. Since we know there are going to be margins for cutting the dies, this seems quite reasonable, no?

That's my thinking too.

 

[ban25]

From the extra die size, see my and OtakingGX last post.
The theafu also said it does have 512Kb.

As has been mentioned, that was an estimate. He also said it has a 256 KB L1 cache, so I wouldn't put much stock in that.

 

[Teasy]

If this is indeed the chip, then it looks to be a straight die shrink. Note the cache sizes are identical: 64 KB Harvard L1, 256 KB unified L2. uarch looks identical.

Obviously its not a straight die shrink, just look at the die size. Gekko would be 11mm^2 on a 90nm process while PowerPC 750CL is 16mm^2 on a 90nm process. That's 50% more transistors all spent on logic (since they both have the same amount of cache). Considering cache took up about 50% of Gekko's core that means 750CL has around twice the amount of logic transistors as Gekko.

Also I'd think that Broadway would be a modified version of 750CL, just as Gekko was a modified version of 750CXe.

 

[theafu]

As has been mentioned, that was an estimate. He also said it has a 256 KB L1 cache, so I wouldn't put much stock in that.

I also said that was unconfirmed at the time too not a gurantee like the 512 L2. If you're going to quote me or mention what I've said try to keep it in context. My L1 numbers are inaccurate, always have been and are labeled or clarified as such. Where I'm getting this info from I know to be rock solid (though misinterpeted) and Matt Cassamasina has used info he had said times to me and others for reporting cube news that pretty much all within the last two months have come true.

 

[Quaz51]

CPU size comparison

 

[Corwin_B]

CPU size comparison

And the end result :

 

[ban25]

Obviously its not a straight die shrink, just look at the die size. Gekko would be 11mm^2 on a 90nm process while PowerPC 750CL is 16mm^2 on a 90nm process. That's 50% more transistors all spent on logic (since they both have the same amount of cache). Considering cache took up about 50% of Gekko's core that means 750CL has around twice the amount of logic transistors as Gekko.

Also I'd think that Broadway would be a modified version of 750CL, just as Gekko was a modified version of 750CXe.

They probably changed the layout, and a shrink will not be totally linear with the feature size anyway. It would be a bad idea to assume the 750CL has "twice the amount of logic" just for such a tiny discrepancy in die size. Maybe the difference is strictly due to fanout?

 

[Fox5]

Is this really Broadway?

That die is tiny! ~16mm^2. The voltage seems high for some reason -- 1.15v on a pea sized 90nm die? I figured it'd be sub 1v... It doesn't seem like it'd matter in any way really, but it jumped out at me for some reason. Power consumption is kind of boggling when you compare it to PS3/X360 (~5 watts for Broadway). Wii looks like it could feasibly be a handheld... especially if it got shrunk to 65nm!

I don't imagine performance is going to be all that sexy when you have a chip the size of a pea. Don't know much about 750CXe/CX though, so I can't answer you're question really.

Well, far lower power envelope than even some sublight notebooks...oh and wasn't Gecko only 4W? I'm surprised Broadway would use more if it is essentially just a die shrunk version.

""To clear things up: the top-of-the-line PPC 750, the 750GX, is the fastest 7xxx PowerPC. It's much faster than Apple's G4 (PPC 744x) at the same frequency. To call it an overclocked G3 would be quite an understatement. IBM's current 750-series PPCs even outperform G5s at the same clock speed, but don't feature 64bit integer processing. The 7xx series still is the mainline PowerPC family, the 8xxx series are special, embedded 7xx chips, and the 970 chips are nothing more than cheap POWER4 spinoffs, initially created for Apple (IBM prefers POWER4 and POWER5 over PPC970 for their own systems). And no, Gekko was no G3, it's only part of the same CPU family. But Gekko, aka PPC 750CXe, had SIMD units similar to Altivec/ VMX, the G3 only had a regular FPU."

One, benchmarks showing the 750 series outperforming G5 clock for clock please....
And what are the standard cache sizes on the 750 cpus?

I really believe that Nintendo intends to go portable with this design, rather soon. Why else stress such a low power design?

It'd be a decent reason for gamecube backwards compatibility as well, make a small handheld with these specs that doesn't feature the wiimote and only plays gamecube minidisks and it can have both gamecube backwards compatibility and play new games. Additionally the wii could play the same games.

Will wii be passively cooled? It seems wierd for nintendo to cripple their console as much as they have if it still requires a fan in the end. (for the case size, I'd imagine a fan is required, but if they made it larger I think a few watts could be dissappated by passive cooling)

That's 50% more transistors all spent on logic (since they both have the same amount of cache).

Perhaps the cache has more associativity or a bigger databus or something along those lines?

CPU size comparison

So uh....broadway versus PPE-SPEs performance?

 

[sfried]

CPU size comparison

Perhaps it would be better if you compared the size with a quarter.

 

[Teasy]

Perhaps the cache has more associativity or a bigger databus or something along those lines?

According to the PDF both caches have the same associativity.

They probably changed the layout, and a shrink will not be totally linear with the feature size anyway. It would be a bad idea to assume the 750CL has "twice the amount of logic" just for such a tiny discrepancy in die size. Maybe the difference is strictly due to fanout?

But 11mm^2 to 16mm^2 isn't a tiny discrepancy in die size, its almost 50%. Also surely layout changes are made to make a chip smaller, not significantly bigger.

There may not be exactly twice the amount of logic, I agree there, but there certainly is a significant amount more than Gekko as far as I can see.

 

[ban25]

11mm^2 to 16mm^2 is hardly a tiny discrepancy in die size, its almost 50%. Also surely layout changes are made to make a chip smaller, not significantly bigger.

Obviously there may not be exactly twice the amount of logic, but there certainly is a significant amount more than Gekko.

Again, just because the feature size has gone from 130nm to 90nm doesn't mean you can expect a linear decrease in size. It's neither obvious nor certain that there is a 'significant' amount of additional logic over Gekko.

Where did you get this 11mm figure, anyway? The PDF clearly states on page 14:

15.92 sq. mm (3.99x3.99mm)

This is for the chip as described in the datasheet.

 

[Teasy]

Again, just because the feature size has gone from 130nm to 90nm doesn't mean you can expect a linear decrease in size. It's neither obvious nor certain that there is a 'significant' amount of additional logic over Gekko.

AFAIK you can expect that, more or less (not linear maybe, but a 50% discrepancy?). Anyway what reason do you have to believe that the discrepancy in die size is not due to extra logic?

 

[Shifty Geezer]

Again, just because the feature size has gone from 130nm to 90nm doesn't mean you can expect a linear decrease in size.

I thought generally that's what happened.

 

[Fox5]

AFAIK you can expect that, more or less (not linear maybe, but a 50% discrepancy?). Anyway what reason do you have to believe that the discrepancy in die size is not due to extra logic?

Honestly, I'd say it's without question that it contains additional logic, just that the logic will make no more than at most a 5% increase per mhz, if any. It could be bug fixes or something similar. Well, there could be a larger performance increase if the logic is for SIMD units, but even then those aren't universally useful.

 

[ban25]

AFAIK you can expect that, more or less (not linear maybe, but a 50% discrepancy?). Anyway what reason do you have to believe that the discrepancy in die size is not due to extra logic?

If it is, it doesn't show it in the datasheet. I'm not seeing any additional FUs here or extra scheduling logic, pipeline stages, etc, that might account for a difference. Since "50% more logic" is your theory, one would think you might do the leg work and read the datasheets for both the 750CL and 750CXe to compare -- since the answer is literally right in front of you.

I think all of the reasons I've given are far more valid (less than 50% reduction in die size from new process, fan-out on such a small core), not to mention the fact that this 11 sqmm figure is a made-up number and is in all likelyhood inaccurate.

 

[ban25]

I thought generally that's what happened.

It will be close to that, but you are talking about the average feature size, so it's not going to be exact depending upon the chip. I'll be honest and say that I can't even believe people are disputing IBM's datasheet because someone's die estimate was off by 5 sqmm.

 

[archie4oz]

One, benchmarks showing the 750 series outperforming G5 clock for clock please....
And what are the standard cache sizes on the 750 cpus?

What benchmarks? I've never even seen anybody test the 970 clocked down to 1GHz, so most assumptions are just extrapolations (which aren't always accurate). I did say that a 750GX could outperform a similar clocked 970 however in some cases, but in no means is it going to trounce on the 970 across the board. In the cases where a 750GX has beaten a 744x at the same clock (e.g. EEBMC tests) it's usually because it's an older 7455 which is running a slower FSB, less aggressive memory timings, and the 7455 having 1/4 the L2 (and no L3). And like I said, there's still cases where it'll still beat a current, similar clocked 7448, but those are quite few and rare (basically anything that exercises the complex int unit a lot, or the the FPU's latency a lot).

 

[darkblu]

oh, while we're on the topic of 'IBM's G3 and likes versus Moto's G4 and G5', some of you might find interesting the following freescale doc dubbed 'Migration from IBM 750FX to MPC7447A' - i found that rather useful.

 

[Fafalada]

The only differences I see in the block diagrams

And those differences are word for word identical to enhancements Gekko received originally.
As noted btw - load/store "Quantization" is a feature essentially identical to the much vaunted "compressed d3d format support" that MS boasted for Xenon (except it's a fused instruction thus faster then 360 implementation), and like Archie mentioned, this has been around in CPUs since PS2 days (included were pack/unpack instructions inside and outside VUs).

This support isn't even in the same class as AltiVec, which is not only far more flexible and applicable in more use cases, but also retains it's own execution resources instead of overlaying the FPU

While that is true(Gekkos extended FP ISA is fairly primitive compared to AltiVec, even before we consider half the throughput etc.) - the dual-FP nature of Gekkos SIMD means free/direct component access and simple access to unaligned data.
So a 4-way SIMD with similar kind of programmer access(well, throw in some enhancements to ISA and mapping of the register set) would be considerably more efficient in FP SIMD(as far as attaining peak performance goes) then Altivec can ever be. - The real world example of which we got circa 2 years ago - just not in an IBM cpu(obviously).