ATI R500 patent for Xenon GPU?

Typically multipliers scale (more or less) quadratically with regards to their bit depth/precision, while adders tend to scale linearly.

However, I suspect most of the die area to be taken up by the multiplier, so I would guess that a 32 bit FMADD would be ~25-35% of the size of a 64 bit FMADD.
 
akira888 -

Staying with 130nm CMOS - how does this area reduction translate to power reduction? Can I scale the power estimate by the roughly the same factor without leaving the ballpark of reality completely?
 
I don't think you can scale power the same as area due to current leakage getting worse with smaller processes.
 
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