Ati following in nvidia's footsteps ?

[digitalwanderer]

Even with the NV3X it wasn`t a blow the doors off situation in terms of immediately apparent performance.

Well on that I'll just have to agree to disagree, but I do agree that I don't really expect that scenerio again anytime soon.

 

[Moloch]

it has way better fsaa.
I still remember [H] saying how much a difference it was when running games.

 

[rwolf]

I wonder how the 850XTPE with the nanocooler will do against the 7800.

 

[Anon Lamer]

Any chance for ATI using a 512 bit bus? It would enable the usage of slower and cheaper memory while still beating the g70 in benchmarks.

 

[Richard]

Any chance for ATI using a 512 bit bus? It would enable the usage of slower and cheaper memory while still beating the g70 in benchmarks.

Perhaps not, because of:

http://www.beyond3d.com/articles/xenos/index.php?p=03

?

 

[Ailuros]

I think the new memory "system" in R520 is ATI's secret weapon. What if it turns out to perform like a 512-bit bus, but is in fact only a 256-bit bus?

Wishful dreaming IMO. While I'm confident that added changes will increase bandwidth efficiency, I have severe doubt it'll ever reach such levels. In a best case scenario it could rather be X% with a up too label (which many might tend to ignore when reading technical whitepapers).

And what if R520 runs at 700MHz core?

Also unlikely considering the leakage rumours. If the part can handle 8 MADDs/cycle, even less than 650MHz is enough to compete.

And what if we get R580, not R520?...

Indications so far point at lacklustering availability for the latter. It makes only sense to release ASAP the R580.

 

[Geo]

I think the new memory "system" in R520 is ATI's secret weapon. What if it turns out to perform like a 512-bit bus, but is in fact only a 256-bit bus?

Wishful dreaming IMO. While I'm confident that added changes will increase bandwidth efficiency, I have severe doubt it'll ever reach such levels. In a best case scenario it could rather be X% with a up too label (which many might tend to ignore when reading technical whitepapers).

Yes, I think Jawed admitted later that maybe he'd gone to his happy place on that one. I *do* like to hear people sign up for increased bandwidth efficiency tho, as the whole "clients" thing could have been read entirely as latency improvements on the back end. From an engineering resources investment pov, what kind of ballpark do you need to get into on "X" before mangement types start blinking their eyes and going "let's do it!"?

Edit: Come to think of it, HDR AA would tend to support the idea they've done something there as well, given the stiff hit on bandwidth involved.

 

[ANova]

ATI could have managed to develop some type of new or altered interface. There is that 2x256 bit rumor.

 

[Geo]

ATI could have managed to develop some type of new or altered interface. There is that 2x256 bit rumor.

I may be getting my rumors mixed up, but I thot that one was an NV rumor?

 

[Moloch]

I call shens on 2x256 or a single 512.
Maybe it's a really effcient 256 bit controllor, and doesn't have problems under certain configs (like how the current memory bus doesn't seeem to work well with the 3 quad cards.

 

[_xxx_]

People, why aren't you able to grasp that 512 bit bus is NOT FEASIBLE UNDER ANY CIRCUMSTANCES today?

If anything, we'll go towards some kind of serial bus in the future, but don't expect 512 bit or 1024 bit anytime soon.

 

[Geo]

I always took "2x256" to be a coy allusion to an IHV reference design of sli/mvp-on-one-card anyway (rather than an AIB take). "Dual-core", when used in graphics context, for that matter as well (i.e. coy allusion). Given the technical limitations, I don't see any other possibility.

 

[rwolf]

People, why aren't you able to grasp that 512 bit bus is NOT FEASIBLE UNDER ANY CIRCUMSTANCES today?

If anything, we'll go towards some kind of serial bus in the future, but don't expect 512 bit or 1024 bit anytime soon.

I am still waiting for an optical bus.

 

[_xxx_]

rwolf, look for MOST/MOST2. It's currently used in cars for multimedia, but the bandwidth is nowhere near what's needed for gfx.

 

[Hellbinder]

            NV30      R300
pixel p.     4         8   
vertex p.    3         4
mem. bus    128bit   256bit

NV30 (compared to R300) had only 50% of pixel pipelines, 75% of vertex pipelines and 50% narrower memory bus

            G70     R520
pixel p.    24       12       ( =G70 - 50%)
vertex p.    8        6       ( =G70 - 25%)
mem. bus   256bit   128bit    ( =G70 - 50%)

Somebody thinks than R520 will be a 128bit 12/6 pipeline graphic card? No? So where is the parallel with NV30? (except its 2-3 months delay)

That second part is just dumb...

G70 doesn't have 24 "pixel" pipelines. and 520 sure as heck does not have 12.

 

[Hellbinder]

Somewhere in the 600mhz range I would say.

 

[Megadrive1988]

doesn't 3DLabs recent P20 VPU have some sort of 2x 256-bit bus configuration (thus initally reported to be a 512-bit bus) ?

 

[no-X]

That second part is just dumb...

G70 doesn't have 24 "pixel" pipelines. and 520 sure as heck does not have 12.

Forget it. I was only a try to show, that comparison of R520 with NV30 isn't good. (R520 won't have halved memory bus and number of pipelines compared to it's competitor).

And pixel pipelines / pixel shader pipelines / fragment pipelines ... depends on terminology (some websites/vendors/chipmakers use "pixel pipeline" as syn. for ROP, others for fragment pipeline :? )

 

[_xxx_]

doesn't 3DLabs recent P20 VPU have some sort of 2x 256-bit bus configuration (thus initally reported to be a 512-bit bus) ?

It's also a two-chip thingy, it's still 256.

 

[neliz]

doesn't 3DLabs recent P20 VPU have some sort of 2x 256-bit bus configuration (thus initally reported to be a 512-bit bus) ?

It's also a two-chip thingy, it's still 256.

THAT fact never stopped a marketing department, right?