ATi CEO Interview

[Natoma]

Remember that TSMC has two .13Micron processes. .

I didn't know they had two, where did you read this? Link?

I think he is referring to the Low-K process (?).

The RV350 is for desktops only, the M10 will be the DX9 notebook chip.

The RV350 IS essentially the M10.

MuFu.

Yes, that's what it was. I remember it had to do with one being a Low-K dialectric process. The more advanced 0.13 Micron process had this, which allowed it to run cooler.

Nvidia and TSMC could not get it working properly, so they went with the less advanced 0.13 Micron Process, which is why the NV30 runs so hot.

 

[KimB]

Well, that's one reason. The other appears to be that they want to run it at 500MHz. It would probably have around half the heat disippation at 400MHz (depending on a variety of factors).

 

[Fuz]

The RV350 IS essentially the M10.

Would I be wrong in saying the RV350 is NOT identical to the M10?
I presumed there were enough differences with the chips to warrant a dif code name.

 

[Ichneumon]

The RV350 IS essentially the M10.

MuFu.

While that's most likely true, when ATI talks about the RV350, they are talking about the desktop chip.

 

[MuFu]

Yep. They have done this kind of thing on the past - RV250~M9, Ripper2=RT2~Theatre200 etc.

MuFu.

 

[Gunhead]

Just in case anybody is wondering...

Low-k di-electric materials are insulators that help prevent electronic interference (crosstalk between tightly packed copper wires) in the chip. Noise reduction, sort of.

 

[Natoma]

Just in case anybody is wondering...

Low-k di-electric materials are insulators that help prevent electronic interference (crosstalk between tightly packed copper wires) in the chip. Noise reduction, sort of.

Am I correct in assuming that this would in turn lower the voltage requirements of a chip created using these materials, and thus help lower the heat output?

 

[Gunhead]

Exactly! (Conversely, CPU overclockers sometimes up the voltage to get the chip stable -- the larger voltage differential helps tell between 1 and 0 when things get fast in a crowded chip.)

So it's a safe bet that the leaf blower was added after the process change ;-)

 

[arjan de lumens]

The voltage requirements of a chip are mostly dictated by transistor threshold and breakdown voltages, having by itself nothing to do with low-k dielectrics. Given that low-k dielectrics improve performance (mostly by reducing interconnect delay) you might be able to attain a desired level of performance at a slightly lower voltage, though - or you may keep up the voltage and squeeze some additional performance out of the part.

 

[overclocked]

IBM´s SOI/silicon on isulator that AMD will use in the hammer family is the same thing roughly.

 

[Evildeus]

BTW,is this common that comments on future chips? (I don't have enough background )

 

[overclocked]

Yes i think it is.
The smaller the process becomes you must find ways to reduce the problems we are talking about.

Intel is going low-k first on 90nm if i remember right.

 

[JonWoodruff]

low-k dielectric, Silicon on Insulator.

Low-k dielectrics actually fill the gap between the gate and the channel
in a transistor and so are VERY related to threshold voltage and switching
speed. For the uninitiated, this part (the gate) of a transistor looks like
a sandwich with metal on top, dielectric (an insulator) in the middle,
and silicon on the bottom. When voltage is applied to the gate it causes
the silicon on the other side of the dielectric to conduct like a wire. The thinner the dielectric the faster it can switch, and switching speed is also
affected by tons of other factors as well (like operating voltage and the
"k" (insulating value) of the dielectric).

Silicon on Insulator keeps charge from leaking away from the whole
transistor so that power is conserved and the chip doesn't heat up so
much. With a SoI process, transistors are built in a shallow "pan" of
silicon on top of an insulator instead of in a deep "ocean" of silicon into
which some charge will leak.

Kapeesh? Now let the informed flame-war continue!

 

[overclocked]

Do we need to say more?

 

[PSarge]

Just speaking from what I've noticed using both the low-K process and the not-low-K (High-K?!) process, the main thing it tends to effect is the capacitance of the interconnect between gates rather than the speed of the transistors themselves. In the libraries the propogation delay of the gates is pretty much unchanged one process to the other, but once you start connecting them to each other you notice the difference.

This means that the gates dont need to be as high strength (draw less current, lower power) on low-k to switch at the same speed as they have smaller capacitors to charge on their outputs. Another way of looking at it is that gates with the same drive strength will switch quicker on the low-K process, as it takes less time to fill a smaller bucket (capacitor)

To summerise:

Low-K = a) Low power at same clock speed or b) same power at higher clock speed.
High-K = c) Higher power at same clock speed or d) same power at lower clock speed.

Looks like nvidia were stuck with the high-K process, so went for option C. Hence the cooling.

 

[arjan de lumens]

Re: low-k dielectric, Silicon on Insulator.

Low-k dielectrics actually fill the gap between the gate and the channel
in a transistor and so are VERY related to threshold voltage and switching
speed. For the uninitiated, this part (the gate) of a transistor looks like
a sandwich with metal on top, dielectric (an insulator) in the middle,
and silicon on the bottom. When voltage is applied to the gate it causes
the silicon on the other side of the dielectric to conduct like a wire. The thinner the dielectric the faster it can switch, and switching speed is also
affected by tons of other factors as well (like operating voltage and the
"k" (insulating value) of the dielectric).

Umm, you've got it backwards. For the gate dielectric, you want the value of k as *high* as possible - this will make the capacitance per area unit higher and thus make it possible to induce the electric field needed to switch on/off the transistor with a smaller voltage and chip area. Using low-k dielectrics for the gate insulator would ruin the performance. Traditionally, the gate dielectric has grown thinner and thinner for each new process generation precisely to increase the capacitance per chip area. IBM, Motorola and doubtlessly Intel, TSMC, etc are intensively researching high-k dielectrics for this particular use.

Low-k dielectrics are used in the higher layers of the chips to insulate conductors from each other and reduce the parasitic capacitiance between them, giving lower RC interconnect delays.