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Apache Design Solutions and ATI Technologies announced that the latter had expanded its world-wide adoption of Apache’s complete dynamic power integrity suite, including RedHawk-EV with PowerGate (low-power ramp-up analysis), NSpice-PI, and recently announced PsiWinder. In a multi-million dollar per year, multi-year agreement, ATI will use Apache’s products for dynamic power and timing sign-off, as well as package-IC interface analysis.
RedHawk is a full-chip Vectorless Dynamic physical power integrity solution for SoC power closure sign-off of 130nm, 90nm, and 65nm designs. Certified by TSMC’s 5.0 Reference Flow and correlated with silicon measurements and SPICE, RedHawk addresses dynamic power issues such as simultaneous switching output (SSO) for core, memory, clock, and I/O, as well as effects of on-chip inductance, package RLC, and decoupling capacitance.
RedHawk enables designers to identify dynamic “hot spotsâ€, examine the impact on timing, accurately pinpoint the cause of dynamic voltage drop, and automatically repair the source of supply noise. With RedHawk’s integrated transistor-level characterization to assure accuracy, designers can reach power closure sign-off for high performance SoCs, including those utilizing advanced low-power design techniques such as leakage current control, power gating, multiple voltage domains, and multiple threshold transistors. The PowerGate option enables RedHawk to analyze the ramp-up, ramp-down transient behavior of power-gated blocks as well as back-biasing impacts.
“We found that Apache has a good vision of where the tools should be going and what kind of problems, we as designers, are facing and trying to address,†said Simon Burke, engineering manager at ATI. “We’ve been using RedHawk for more than a year on our most advanced production designs and we've been very pleased with its ability to accurately analyze the impact of dynamic voltage drop of our chips. We’re also impressed with Apache’s ability to deliver robust and on-time solutions for our unique enhancement requests.â€
“Moving forward, we will continue to work with Apache to broaden our deployment and address emerging challenges such as global I/O SSO,†continued Burke. “Recently, we evaluated PsiWinder for combined power and signal integrity critical path timing analysis, including the clock tree. By using PsiWinder we were able to dramatically shorten and automate our SPICE netlist extraction, setup, and simulation time. This not only significantly increases the number of paths we can analyze per day but also improves our productivity.â€
News Source: X-bit Labs
RedHawk is a full-chip Vectorless Dynamic physical power integrity solution for SoC power closure sign-off of 130nm, 90nm, and 65nm designs. Certified by TSMC’s 5.0 Reference Flow and correlated with silicon measurements and SPICE, RedHawk addresses dynamic power issues such as simultaneous switching output (SSO) for core, memory, clock, and I/O, as well as effects of on-chip inductance, package RLC, and decoupling capacitance.
RedHawk enables designers to identify dynamic “hot spotsâ€, examine the impact on timing, accurately pinpoint the cause of dynamic voltage drop, and automatically repair the source of supply noise. With RedHawk’s integrated transistor-level characterization to assure accuracy, designers can reach power closure sign-off for high performance SoCs, including those utilizing advanced low-power design techniques such as leakage current control, power gating, multiple voltage domains, and multiple threshold transistors. The PowerGate option enables RedHawk to analyze the ramp-up, ramp-down transient behavior of power-gated blocks as well as back-biasing impacts.
“We found that Apache has a good vision of where the tools should be going and what kind of problems, we as designers, are facing and trying to address,†said Simon Burke, engineering manager at ATI. “We’ve been using RedHawk for more than a year on our most advanced production designs and we've been very pleased with its ability to accurately analyze the impact of dynamic voltage drop of our chips. We’re also impressed with Apache’s ability to deliver robust and on-time solutions for our unique enhancement requests.â€
“Moving forward, we will continue to work with Apache to broaden our deployment and address emerging challenges such as global I/O SSO,†continued Burke. “Recently, we evaluated PsiWinder for combined power and signal integrity critical path timing analysis, including the clock tree. By using PsiWinder we were able to dramatically shorten and automate our SPICE netlist extraction, setup, and simulation time. This not only significantly increases the number of paths we can analyze per day but also improves our productivity.â€
News Source: X-bit Labs
