IHVs are transitioning to 90nm that allows twice as many transistors at the same die size than 130nm.
So - will they double the number of pipes with the same memory interface?
Unlikely - there's not enough bandwidth.
So - will they go to 512 bit?
Unlikely - that would require a huge die to connect all the wires.
So - we need faster memory access and transistors to spare...
What about increasing the on-die memory? (texture cache, Z-cache, reduced size Z buffer, etc...)
So - will they double the number of pipes with the same memory interface?
Unlikely - there's not enough bandwidth.
So - will they go to 512 bit?
Unlikely - that would require a huge die to connect all the wires.
So - we need faster memory access and transistors to spare...
What about increasing the on-die memory? (texture cache, Z-cache, reduced size Z buffer, etc...)
