Apple A9 SoC

[iMacmatician]

Rumours coming out of china point to a 2 plus 2 cpu design, not unlike big little. One low power cluster running at 1.2ghz and the high powered cluster running at 1.7ghz, with 2 gig ram.
Couple of thoughts, die would be massive If using cyclone for all cores would it not? Unless using a53s in traditional ARM style.._so un apple like.
Wffctech

9to5Mac got a tip with the same core configuration last month. 2+2 design double confirmed?

If the Geekbench scores of 1921 single-core and 4873 multi-core in the linked report are true, then that's one way to get +70%: 4873/2882 = 1.69.

 

[french toast]

9to5Mac got a tip with the same core configuration last month. 2+2 design double confirmed?

If the Geekbench scores of 1921 single-core and 4873 multi-core in the linked report are true, then that's one way to get +70%: 4873/2882 = 1.69.

Yea that does make a lot of sense, i dont think anyone really believes you can increase single thread by 70% in a single year, not when they were already the leader in that regard even now, had to be some multhreaded sauce going on, i believed we would of seen some form of SMT, but a couple of optimized a53s would be miles better, especially if all 4 can be used at once.
Still a big IF though.

*Multithreaded.

 

[french toast]

.
The Apple Watch uses a customized Cortex A7 core running armv7k. Apple could build a customized A53 core that can serve on its own in a future Apple Watch or be used as a companion core in iPhones/iPads so they can have a core meeting their needs without splitting their resources on too many designs.

Yes this also seems sensible , a53s would seem a great fit for iwatch, the question is what setup would they use for a9x?

 

[Turbotab]

Yes this also seems sensible , a53s would seem a great fit for iwatch, the question is what setup would they use for a9x?

But the A53 is more power hungry than than the A7,on the same process node, as evidenced in this informative Anandtech article. It's also a larger core, and in something as space and power constrained as the Apple Watch, that may be critical.
http://www.anandtech.com/show/8718/the-samsung-galaxy-note-4-exynos-review/4

Back on topic, I believe that if the quoted Geekbench figures are correct (if!), and given the core scaling of the A8 & A8X, then it's rational to assume that the A9 will be a tri-core SoC in the 1.5 to 1.6 GHz range. I doubt that Apple have kept a wide core design and significantly increased clock speed to the 2 GHz range that a purported dual-core benchmark stated, because even with a move to FinFets the extra voltage required for much higher clocks would increase overall power requirements, and given that Apple have fitted the 6s with a smaller battery that seems unlikely. OK, LPDDR4 is more power efficient, but they hopefully will have more of it, so no saving there. The screen may be a lot more efficient, but that seems unlikely, and Forcetouch must have an impact on battery life, even if it's small.

Rumoured perf numbers, possibly BS!
http://9to5mac.com/2015/08/14/opinion-what-to-expect-from-apples-a9-chip/
A8 - Single core = 1610 / Dual core = 2890 (Scaling 1 to 2 cores = 1.795x)
A9 - single core = 1921 / X core = 4873 (Scaling 1 to x cores = 2.53x)

The A9 multi -core score scaling is also the same as the A8X, which achieves a 2.5x increase from 1 to 3 cores, which is interesting.

The ideal of a 2+2 SoC of 1.7 GHz and 1.2 GHz does not seem to fit. If we ramp the clock of the A8 by 20% and take the 1 to 2 core scaling from the iPhone 6, it gives us a figure of ~3450, which leaves a shortfall of 1400 hundred points. If the low-power cores @ 1.2 GHz were cyclone based, it would easily exceed that score, but is that likely or logical, in terms of power consumption. If the extra 2 cores are based on ARM's A53 @ 1.2 GHz they would not contribute enough performance to achieve the extra 1400 points needed. The quad-core Snapdragon 410 ( ARM A53) in the Moto E 2nd gen, only achieves a Geekbench 3 score of 1486 for the entire phone!

 

[iMacmatician]

So “Twister” is the core codename?

Also, do you know anything else about the core?

 

[oscarbg]

Rys, can you talk A9X is 3 twister cores or 4?
also can talk if A9 GPU is based on Series7XT so compute perf enhancements and better yet supports all of Android extensions pack in hardware, i.e. tesselation, geometry shaders,etc..

 

[Entropy]

If the A9 improves its dual core performance with 70% over the A8 in the same form factor, then the A9x cores increasing 80% over the A8x is not unreasonable with larger body to heatsink to, and larger battery both facilitating a bit higher power draw.
How on earth they got 70% higher performance per core on the A9 in the first place is the greater mystery!

 

[anexanhume]

If the A9 improves its dual core performance with 70% over the A8 in the same form factor, then the A9x cores increasing 80% over the A8x is not unreasonable with larger body to heatsink to, and larger battery both facilitating a bit higher power draw.
How on earth they got 70% higher performance per core on the A9 in the first place is the greater mystery!

Maybe we are in order for another large clock boost. A5 to A6 was 62.5% boost. 1.8GHz would be 30% alone. Another 30% IPC boost would do it. Not to say that's trivial at all.

 

[Ailuros]

Would the same reasoning be in place this time as last time ? In series 6, they had nothing public that could do 2*6450. IMG have public 7XT IP that can hit the performance of 2*GT7600. An upclocked 7800 could easily do it, and given the much bigger chassis, upclocking would be very possible. I guess it depends on how much die-space they want to use, in that chip

Apple traditionally prefers to go wider with conservative frequencies especially for GPUs. My expectations for quad and octa cluster GPU in A9/A9X with modest frequency increases would give also more modest performance increases compared to 6/12 clusters somewhere around 500+MHz hypothetically.

 

[rapso]

The A7 was 2 x 32-bit LPDDR3, the A8 was 2 x 32-bit LPDDR3, and the A8X was 4 x 32-bit LPDDR3. Apple hasn't used a single channel memory controller since the A4.

I was reading that in several magazines (unless my brain mixes up things). lets see if I can find sources...

wiki seems to agree with my memory: https://en.wikipedia.org/wiki/Apple_system_on_a_chip#.22Ax.22_series_2

 

[rapso]

Apple did say they doubled memory bandwidth, and we know it's 128bit (really 4x32bit) LPDDR4.
This, however, will do nothing for cpu performance. Unless you measure memcpy (and even then I'm actually sceptical the cpu cores can actually saturate all the bandwidth).

cpu performance nowadays mostly depend on memory, that's why L3 caches arised on A7 (and L4 on desktop).

They've improved the CPU performance going from A7->A8 already quite a lot without increasing the bandwidth.
you might not saturate 50gb on a single core, but they haven't said 80% IPC boost, but CPU, that means it's valid to assume all 2 or 3 cores running at full load and in that case you can gain a lot if you double the bandwidth and maybe increase the caches (and maybe improve memory pre-fetching).

I think they've said the A9 (iphone 6s) will be 70% faster over the previous generation, in that case it could be quite alike the A8x. The A9x might be another configuration (e.g. more cores).

 

[ltcommander.data]

I was reading that in several magazines (unless my brain mixes up things). lets see if I can find sources...

wiki seems to agree with my memory: https://en.wikipedia.org/wiki/Apple_system_on_a_chip#.22Ax.22_series_2

I guess you're right. I didn't know that LPDDR3 was now natively 64-bit rather than 2x32-bit.

 

[Nebuchadnezzar]

I guess you're right. I didn't know that LPDDR3 was now natively 64-bit rather than 2x32-bit.

That seems outright wrong. You actually detriment performance by going wider single channel. Also keep in mind most times when talking actual memory channels it's actually 2x2x16bit for dies.

 

[Grall]

A bit off-topic perhaps )), but which sci-fi movie was it we saw short clips from during the recent presentation, Prometheus II maybe? I've been trying to goggle it, but this seems one of those instances where you get nothing but irrelevant search results regardless of input. Maybe nobody simply commented on it online and there's subsequently nothing to find.

Bring on AI Agents for finding information independently, I say!

 

[Rys]

A bit off-topic perhaps )), but which sci-fi movie was it we saw short clips from during the recent presentation, Prometheus II maybe? I've been trying to goggle it, but this seems one of those instances where you get nothing but irrelevant search results regardless of input. Maybe nobody simply commented on it online and there's subsequently nothing to find.

Bring on AI Agents for finding information independently, I say!

The Martian.

 

[french toast]

But the A53 is more power hungry than than the A7,on the same process node, as evidenced in this informative Anandtech article. It's also a larger core, and in something as space and power constrained as the Apple Watch, that may be critical.
http://www.anandtech.com/show/8718/the-samsung-galaxy-note-4-exynos-review/4

Back on topic, I believe that if the quoted Geekbench figures are correct (if!), and given the core scaling of the A8 & A8X, then it's rational to assume that the A9 will be a tri-core SoC in the 1.5 to 1.6 GHz range. I doubt that Apple have kept a wide core design and significantly increased clock speed to the 2 GHz range that a purported dual-core benchmark stated, because even with a move to FinFets the extra voltage required for much higher clocks would increase overall power requirements, and given that Apple have fitted the 6s with a smaller battery that seems unlikely. OK, LPDDR4 is more power efficient, but they hopefully will have more of it, so no saving there. The screen may be a lot more efficient, but that seems unlikely, and Forcetouch must have an impact on battery life, even if it's small.

Rumoured perf numbers, possibly BS!
http://9to5mac.com/2015/08/14/opinion-what-to-expect-from-apples-a9-chip/
A8 - Single core = 1610 / Dual core = 2890 (Scaling 1 to 2 cores = 1.795x)
A9 - single core = 1921 / X core = 4873 (Scaling 1 to x cores = 2.53x)

The A9 multi -core score scaling is also the same as the A8X, which achieves a 2.5x increase from 1 to 3 cores, which is interesting.

The ideal of a 2+2 SoC of 1.7 GHz and 1.2 GHz does not seem to fit. If we ramp the clock of the A8 by 20% and take the 1 to 2 core scaling from the iPhone 6, it gives us a figure of ~3450, which leaves a shortfall of 1400 hundred points. If the low-power cores @ 1.2 GHz were cyclone based, it would easily exceed that score, but is that likely or logical, in terms of power consumption. If the extra 2 cores are based on ARM's A53 @ 1.2 GHz they would not contribute enough performance to achieve the extra 1400 points needed. The quad-core Snapdragon 410 ( ARM A53) in the Moto E 2nd gen, only achieves a Geekbench 3 score of 1486 for the entire phone!

Yea i had read that article previously , i thought the whole idea of a53s was to underclock them compared to a7s( obviously stll increasing performance due to higher IPC).Smart watches already contain snapdragon 400 with 4 a7s, i dont think 2 a53s clocked appropriately would not do the job.

 

[french toast]

Rys, can you talk A9X is 3 twister cores or 4?
also can talk if A9 GPU is based on Series7XT so compute perf enhancements and better yet supports all of Android extensions pack in hardware, i.e. tesselation, geometry shaders,etc..

A9 is dual Twister cores.

If this is the case and there are no other smaller cores, then im going for some kind SMT solution with some turbo/boost frequency ala Intel. That would be a good fit for apple, i stilll prefer the 2 plus 2 approach though.

 

[mczak]

cpu performance nowadays mostly depend on memory, that's why L3 caches arised on A7 (and L4 on desktop).

They've improved the CPU performance going from A7->A8 already quite a lot without increasing the bandwidth.
you might not saturate 50gb on a single core, but they haven't said 80% IPC boost, but CPU, that means it's valid to assume all 2 or 3 cores running at full load and in that case you can gain a lot if you double the bandwidth and maybe increase the caches (and maybe improve memory pre-fetching).

CPU performance is not all _that_ dependent on memory bandwidth - you definitely do need caches but they are mostly about latency. Just think about it, even if you assume those new cores have the same IPC as intel's latest desktop cores, something like a i7-4790k still has 3 times or so the performance of a A9x (one core more, and twice the clock or so) and all that with the same bandwidth the A8X already had. Skylake now has more bandwidth than that but if you look at tests the difference this makes is quite tiny (for the cpu alone).

 

[rapso]

@mczak, I admit, that sounds quite convincing for the general performance. yet, I think the 70% are rather peak numbers. benchmarking something memory limited could be the simplest way to achieve that. but I'm not saying there aren't other improvements, I'd think it's quite likely they use something alike the A8 in the iPad2. (for the phone).

 

[rapso]

That seems outright wrong. You actually detriment performance by going wider single channel.

I'm not sure how exactly the mapping between addresses to the actual chips works in multi channel controllers, but why would you detriment performance as long as the bus with is < of a cache line size?

the scenarios I can think of are: if addresses are interleaved by more than cache line width, then you'll be able to have twice the fetches in-flight, but every single fetch that potentially stalls a core would take a bit longer to finish and as good as chances are that two fetches address different channel, you have the same chance that two fetches stall on the same channel while the other is idle. (there is also the trivial case where both channels interleave with <cache line size, but then there would be no benefit at all, I assume).

On the other side, less channels simplifiy the controller probably, maybe the saving allows a higher clocked soc overall? It leads to simpler scheduling of requests (otherwise you have some kind of crossbar or node-bus to communicate between x cores and n controller).

what scenario would benefit from dual channel with the same bandwidth as a single channel design?

I think I was reading somewhere that one of the reason might be the increased cache line size (32byte -> 64byte) but that's in some foggy area of my brain.