Andrei, how did you run SPEC on little cores?Still need some time, sorry.
BTW, how could I run Dhrystone/Geekbench5 on L/B cores?
Andrei, how did you run SPEC on little cores?Still need some time, sorry.
Comparing to the A12 die of last year, that would be top left to right:
I've updated my piece with the die shot analysis and IP block size breakdown:
https://www.anandtech.com/show/14892/the-apple-iphone-11-pro-and-max-review/2
You probably are right, some digging shows TSMC 7nm can do up to 256 MB on 42.64 mm2.You can’t do that sort of analysis, different kinds of circuitry (logic, memory, I/O) all have different densities. Not only that, but for instance SRAM with different performance characteristics have different density as well, and that is also the case for the other circuitry. (Which is one of the reasons HP designs are less dense than LP.)
The single "density" figure of merit attached to a process node is, unsurprisingly for such a complex subject, largely useless.
I recently converted a program I wrote from node.js to C++. It's a simple procedure for checking the type of a 7-card hand (pair, two pairs, straight, etc.).
To test the procedure, I wrote a tester program to iterate all possible 7-card hands (there are ~154 million distinct hands) to run the procedure. Out of curiosity, I ran the procedures on three different computers (all single threaded):
My MacBook Pro (Intel Core i5-4288U, Apple clang 11): 22.5 seconds
A staging server (Intel Core i5-8500, clang 3.4.2): ~14 seconds
My iPhone 11 Pro (Apple A13, Apple clang 11): 13.8 seconds
This procedure is purely ALU bound with very little memory access, but it's still kind of surprising to see A13 running about as fast as an average desktop CPU from last year in a single threaded workload.
Could you run your test for 5 minutes in a loop and see how that affects timings ?
As you do little memory access, I would be surprised if you see a difference.
The A10x was actually the first 10nm SoC Apple produced, so there is a precedent if the A??x uses 5nm lithography. It would also make sense if a new iPad Pro SoC used LPDDR5.There are rumors, that Apple will release an updated iPad Pro with triple camera in H1/2020 (real next gen iPad then in H2/20 or later). So, what SoC would use this rumored iPad Pro?
Yup, but that doesn't imply anything solid regarding SoCs.There are rumors they release one in the spring and another one in he fall or winter with 5G baseband.
Not quite sure what you're saying here. Of course the next iPhone will have a new SoC, but I don't follow what that implies for an iPad released before September. Or even after, the current baseline iPad is a rather shocking reminder of that.They will have a new SOC because iPhone drives development, not iPad.
They already have some rather nice capabilities for that on-chip, so I'd assume that to continue particularly since higher density lithography gives them more gates to play with. I have some hopes for a dedicated TOF-sensor. And if they include 802.11ay, then I'll buy for sure. But - we are talking iPhone here, not iPad. It is way more opaque where they are heading with those.They’re going to push computational photography so there will be silicon for that, either in the SOC or separately, I’m not sure.