Apple A13 SoC

Andrei, how did you run SPEC on little cores?
BTW, how could I run Dhrystone/Geekbench5 on L/B cores?

 

Source
Apple A13 die size (die seal edge) is 10.67mm x 9.23mm = 98.48 mm2
A13 die shot:

 

Comparing to the A12 die of last year, that would be top left to right:
NPU, next 2x big CPUs, 4 MB L2, 8MB L3 and GPU right
Centrally 4x little CPUs with 2MB L2
Edit: exact size of cache not clear, Nebu thinks it's twice...

 

I've updated my piece with the die shot analysis and IP block size breakdown:

https://www.anandtech.com/show/14892/the-apple-iphone-11-pro-and-max-review/2

 

The estimate of 16 MB for the L3/SLC cache does not seem correct.
By your measurement the 16 MB SRAM takes 6.36 mm2, so fitting 98.48/6.36 = 15.5 times.
If the whole chip would be SRAM, that would fit 248 MB.
A SRAM bit takes 6 transistors, and a byte 8x6, for a total of 248Mx8x6 = 11,89 B transistors.
And we know the A13 has only 8.5 B transistors.

 

You can’t do that sort of analysis, different kinds of circuitry (logic, memory, I/O) all have different densities. Not only that, but for instance SRAM with different performance characteristics have different density as well, and that is also the case for the other circuitry. (Which is one of the reasons HP designs are less dense than LP.)

The single "density" figure of merit attached to a process node is, unsurprisingly for such a complex subject, largely useless.

 

You probably are right, some digging shows TSMC 7nm can do up to 256 MB on 42.64 mm2.
https://en.wikichip.org/wiki/7_nm_lithography_process

 

Out of curiosity, is there some up-to-date data about Intel and AMD core sizes?

EDIT:

I found the Sunny Cove core area here : https://en.wikichip.org/wiki/intel/microarchitectures/sunny_cove#Die

They say 6.91 mm² but that includes private L2 plus the dedicated part of the L3.
Four cores with the ring bus are 30.73 mm².

 

I recently converted a program I wrote from node.js to C++. It's a simple procedure for checking the type of a 7-card hand (pair, two pairs, straight, etc.).
To test the procedure, I wrote a tester program to iterate all possible 7-card hands (there are ~154 million distinct hands) to run the procedure. Out of curiosity, I ran the procedures on three different computers (all single threaded):

My MacBook Pro (Intel Core i5-4288U, Apple clang 11): 22.5 seconds
A staging server (Intel Core i5-8500, clang 3.4.2): ~14 seconds
My iPhone 11 Pro (Apple A13, Apple clang 11): 13.8 seconds

This procedure is purely ALU bound with very little memory access, but it's still kind of surprising to see A13 running about as fast as an average desktop CPU from last year in a single threaded workload.

 

I hope Apple will soon announce a Mac Mini with an ARM processor.
Currently I'm thinking of buying a Surface-X but the A76 is no match yet for A12/13.
( the A76 is not all bad as it has higher Spec2006 per Watt than the A13)
On my iPad Pro I can not install windows, which I hope would be possible on an ARM Mac Mini.

 

Could you run your test for 5 minutes in a loop and see how that affects timings ?
As you do little memory access, I would be surprised if you see a difference.

 

Yeah, it'd be interesting to see if it's possible to reach the SoC's thermal limit when running on only one thread.
I also have a threaded version which can take advantage of multiple cores.
Unfortunately, I updated my iPhone 11 Pro to the latest iOS yesterday and now my XCode does not recognize it so further testing will have to wait after the release of XCode 11.2.

 

Xcode 11.2 is released so I made some new tests by running the same procedure 25 times:

My iPhone 11 Pro (Apple A13, Apple clang 11): 353.82 seconds (14.15 seconds on average)

Multithread version:

My iPhone 11 Pro (Apple A13, Apple clang 11): 169.33 seconds (6.77 seconds on average)