Apple A13 SoC

Source
Apple A13 die size (die seal edge) is 10.67mm x 9.23mm = 98.48 mm2
A13 die shot:
iPhone-11-Pro-A13-Bpoly.jpg
 
Source
Apple A13 die size (die seal edge) is 10.67mm x 9.23mm = 98.48 mm2
A13 die shot:
iPhone-11-Pro-A13-Bpoly.jpg
Comparing to the A12 die of last year, that would be top left to right:
NPU, next 2x big CPUs, 4 MB L2, 8MB L3 and GPU right
Centrally 4x little CPUs with 2MB L2
Edit: exact size of cache not clear, Nebu thinks it's twice...
 
Last edited:
I've updated my piece with the die shot analysis and IP block size breakdown:

https://www.anandtech.com/show/14892/the-apple-iphone-11-pro-and-max-review/2

The estimate of 16 MB for the L3/SLC cache does not seem correct.
By your measurement the 16 MB SRAM takes 6.36 mm2, so fitting 98.48/6.36 = 15.5 times.
If the whole chip would be SRAM, that would fit 248 MB.
A SRAM bit takes 6 transistors, and a byte 8x6, for a total of 248Mx8x6 = 11,89 B transistors.
And we know the A13 has only 8.5 B transistors.
 
You can’t do that sort of analysis, different kinds of circuitry (logic, memory, I/O) all have different densities. Not only that, but for instance SRAM with different performance characteristics have different density as well, and that is also the case for the other circuitry. (Which is one of the reasons HP designs are less dense than LP.)

The single "density" figure of merit attached to a process node is, unsurprisingly for such a complex subject, largely useless.
 
You can’t do that sort of analysis, different kinds of circuitry (logic, memory, I/O) all have different densities. Not only that, but for instance SRAM with different performance characteristics have different density as well, and that is also the case for the other circuitry. (Which is one of the reasons HP designs are less dense than LP.)

The single "density" figure of merit attached to a process node is, unsurprisingly for such a complex subject, largely useless.
You probably are right, some digging shows TSMC 7nm can do up to 256 MB on 42.64 mm2.
https://en.wikichip.org/wiki/7_nm_lithography_process
 
I recently converted a program I wrote from node.js to C++. It's a simple procedure for checking the type of a 7-card hand (pair, two pairs, straight, etc.).
To test the procedure, I wrote a tester program to iterate all possible 7-card hands (there are ~154 million distinct hands) to run the procedure. Out of curiosity, I ran the procedures on three different computers (all single threaded):

My MacBook Pro (Intel Core i5-4288U, Apple clang 11): 22.5 seconds
A staging server (Intel Core i5-8500, clang 3.4.2): ~14 seconds
My iPhone 11 Pro (Apple A13, Apple clang 11): 13.8 seconds

This procedure is purely ALU bound with very little memory access, but it's still kind of surprising to see A13 running about as fast as an average desktop CPU from last year in a single threaded workload.
 
I hope Apple will soon announce a Mac Mini with an ARM processor.
Currently I'm thinking of buying a Surface-X but the A76 is no match yet for A12/13.
( the A76 is not all bad as it has higher Spec2006 per Watt than the A13)
On my iPad Pro I can not install windows, which I hope would be possible on an ARM Mac Mini.
 
I recently converted a program I wrote from node.js to C++. It's a simple procedure for checking the type of a 7-card hand (pair, two pairs, straight, etc.).
To test the procedure, I wrote a tester program to iterate all possible 7-card hands (there are ~154 million distinct hands) to run the procedure. Out of curiosity, I ran the procedures on three different computers (all single threaded):

My MacBook Pro (Intel Core i5-4288U, Apple clang 11): 22.5 seconds
A staging server (Intel Core i5-8500, clang 3.4.2): ~14 seconds
My iPhone 11 Pro (Apple A13, Apple clang 11): 13.8 seconds

This procedure is purely ALU bound with very little memory access, but it's still kind of surprising to see A13 running about as fast as an average desktop CPU from last year in a single threaded workload.

Could you run your test for 5 minutes in a loop and see how that affects timings ?
As you do little memory access, I would be surprised if you see a difference.
 
Last edited:
Could you run your test for 5 minutes in a loop and see how that affects timings ?
As you do little memory access, I would be surprised if you see a difference.

Yeah, it'd be interesting to see if it's possible to reach the SoC's thermal limit when running on only one thread.
I also have a threaded version which can take advantage of multiple cores.
Unfortunately, I updated my iPhone 11 Pro to the latest iOS yesterday and now my XCode does not recognize it :( so further testing will have to wait after the release of XCode 11.2.
 
Xcode 11.2 is released so I made some new tests by running the same procedure 25 times:

My iPhone 11 Pro (Apple A13, Apple clang 11): 353.82 seconds (14.15 seconds on average)

Multithread version:

My iPhone 11 Pro (Apple A13, Apple clang 11): 169.33 seconds (6.77 seconds on average)
 
Does anyone know if any Apple device supports AV1 yet, especially have hardware decoding support?

Initial release according to the Wiki was in March 2018. But maybe those were just specs and it will take awhile to build support in the silicon.

Does A13 have support?

I'm not even sure if there's any content with AV1 encodes yet.


I guess Apple TV 4K doesn't have it. One benefit of a successor Apple TV would be if Apple and Google both support it and Youtube app. would finally have 4K and HDR support on Apple devices.
 
There are rumors, that Apple will release an updated iPad Pro with triple camera in H1/2020 (real next gen iPad then in H2/20 or later). So, what SoC would use this rumored iPad Pro?
The A10x was actually the first 10nm SoC Apple produced, so there is a precedent if the A??x uses 5nm lithography. It would also make sense if a new iPad Pro SoC used LPDDR5.
Basically, no one not constrained by NDAs know what SoC the new iPads will use.
 
There are rumors they release one in the spring and another one in he fall or winter with 5G baseband.
 
There are rumors they release one in the spring and another one in he fall or winter with 5G baseband.
Yup, but that doesn't imply anything solid regarding SoCs.
There has to be a reason to update the iPad Pro SoC at all and personally I'd say that unless they move to 5nm and LPDDR5, they might as well not bother - a widened A13 doesn't offer a whole lot over the A12x. (By mobile standards.)
(Actually, the device that really needs a new SoC is the baseline iPad. Introducing it in the autumn of 2019 with a phone SoC from three generations (!) back was a horrible decision.)
 
They will have a new SOC because iPhone drives development, not iPad.

They’re going to push computational photography so there will be silicon for that, either in the SOC or separately, I’m not sure.
 
They will have a new SOC because iPhone drives development, not iPad.
Not quite sure what you're saying here. Of course the next iPhone will have a new SoC, but I don't follow what that implies for an iPad released before September. Or even after, the current baseline iPad is a rather shocking reminder of that.

They’re going to push computational photography so there will be silicon for that, either in the SOC or separately, I’m not sure.
They already have some rather nice capabilities for that on-chip, so I'd assume that to continue particularly since higher density lithography gives them more gates to play with. I have some hopes for a dedicated TOF-sensor. And if they include 802.11ay, then I'll buy for sure. But - we are talking iPhone here, not iPad. It is way more opaque where they are heading with those.
 
Back
Top