Apple A13 SoC

Discussion in 'Mobile Devices and SoCs' started by iMacmatician, Nov 26, 2018.

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  1. iMacmatician

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    The Twitter user Longhorn (@never_released) has information about the A13.
    Links: [1] [2] [3]

    There is discussion on the Real World Tech forums about these details including the potential implications of the core codenames. Neither codename is about wind so maybe they indicate larger architectural changes than the past five generations?
     
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  2. wco81

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    Apple is in big need of ew tentpole features to drive device upgrades. Unless hardware tracing helps deliver some whiz bang new feature, may not be the best use of R&D.

    Apple needs to find way to deliver products at lower price points. iPhone XS and XS Max sales may show they can't charge whatever they want.

    An Apple SOC in a Mac laptop may deliver better performance than low end Intel chips but they're going to need to lower costs so they can lower prices.
     
  3. AlBran

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    How about a phone based on the 4S shell with upgraded screen and internals? :p Something with actual grip and thickness for battery and lenses too :rolleyes: The new screen types would probably put the 4S chassis at the size close to the viewable area of the 5/6. *cough*

    sigh duck.

    Anyways.
     
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  4. wco81

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    I'm just saying the days of "cost no object" in SOC design and production may be coming to an end for Apple.
     
  5. AlBran

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    Right, just rolling my eyes at apple :p
     
  6. iMacmatician

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  7. Rys

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    Highly likely the one to the bottom right of that that's mostly square. The 2:1 is probably the modem.
     
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  8. Pressure

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    Most likely the one with the highest ball grid arrays. After all, it has the highest I/O.
     
  9. iMacmatician

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    Can the SoC die size be estimated from the squarish rectangle?
     
  10. Rys

    Rys PowerVR
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    Nope, all you get is the package size because the pad distribution is completely regular and holds no clues.
     
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  11. iMacmatician

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  12. Arnold Beckenbauer

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    2+4 and 4 GPU cores.
     
  13. anexanhume

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    Wonder what “high bandwidth cache”, “advanced silicon packaging” and “high bandwidth unified memory” mean from the feature mosaic.
     
  14. Entropy

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    The GPU has some new capabilities that might be of interest. There’s a tech talk video at Apples developer site.
     
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  15. ToTTenTranz

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    High Bandwidth Cache is probably just a larger L3, and High Bandwidth Unified Memory is probably just LPDDR4X 4266MT/s.
    Had they gone with LPDDR5 I think they'd boost up the GPU performance a bit more than 20% and they'd need less L3 for the GPU.
     
  16. Laurent06

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  17. Entropy

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    Geekbench 5 result.
    I really miss the memory benchmark numbers of GB4 (and also feel that they belong in a single FigureOfMerit number if such a number is provided, and it is.)
    If GB reads the cache sizes correctly (GB4 above) there is an interesting story to be told there.
    I wonder how the new floating point capabilities of the CPU will be accessed.
    Also, since they haven’t done the switch to LPDDR5 yet, there is some extremely low hanging performance fruit hanging around for future models.
     
  18. Nebuchadnezzar

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    The memory numbers being gone is a good thing because testing memory is a lot more complicated than a single figure. Too much inaccuracy or score weighing was going on.

    I'll have my more expansive mem test for the AT review.
     
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  19. Laurent06

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    The hypothesis is that these are the cache sizes of the little core. I guess we'll have to wait for Andrei review to be sure :)
     
  20. anexanhume

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    This is unfortunate
     
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