AMD: Zen 2 (Ryzen/Threadripper 3000?, Epyc 8000?) Speculation, Rumours and Discussion

That's how the arrangement looks like:

 

Zen 2 info from today's AMD presentation was interesting. Should be a great upgrade.

On a GPU front, I did not find 7nm Vega to be interesting. They just optimized it a lot for professional use. The wait for Navi continues.

 

Another angle:

 

Does the MI50 provide the first real world suggestion of next gen transistor count? 13.2bn on a 331mm² chip.

 

And another one. Someone should train an AI the can reduce the margin of error on the die's edges in not-so-optimal fotos....

 

Expanding on this a bit, the "chiplet" architecture for Epyc also caught my attention. Is a next-gen console with standalone CPU and GPU chiplets connected to a shared IO hub chip on a MCM plausible?

 

No matter how you measure, that io die is HUGE. Looks like the io is about the same size as all 64 cores put together.

I wonder how much cache it contains.

 

Using dodgy Photoshop measuring:

Chiplet -- 71 mm²
I/O Hub -- 442 mm²

Assuming the package is the same as FCLGA-4094 for the current EPYC series (58.5 mm × 75.4 mm).

 

My result is very close, 73 mm² / 434 mm². Despite the huge 14nm central core, core to mm² ratio is still 67 % better compared to original Epyc.

 

Even the Rome IO die doesn’t have the necessary bandwidth for GDDR6. They have to solve that and prove latency won’t kill performance.

 

Comparing the diagram that was shown first to the MCM picture indicates the IO die has 4 DDR channels on the top and bottom edge. The left and right sides have a pair of infinity fabric blocks next to each corner, with the middle third of the IO die's side given over to a non-differentiated IO block.
Elsewhere, it's been stated that Rome has adopted PCIe 4.0.

The CPU chips are grouped in an interesting fashion compared to the prior EPYC layout. In each quadrant of the MCM, there is a pair of CPU chiplets with much less space between them than there is between them and the IO die, and between them and the nearest chiplet pair below them.
The horizontal midline of the package may be wider partly from the path the IO must take from the central die to the left and right sides.

The lack of space between CPU pairs could mean there's a different topology than previously--and perhaps not as uniform as proposed earlier, if there's short-range links between them and the die nearest the IO chip is connected to both fabric links. While that may introduce an incremental amount of additional latency to the other die, this could give each die more overall bandwidth than giving each CPU chip one link to the IO block. If scaling the PCIe 4.0 bandwidth means xGMI is similarly double-bandwidth, raising the bandwidth of the on-package links to match would give each CPU pair enough link bandwith to utilize all 8 channels in some peak demand situation.

Another possibility is the midline gap is broader in part to let each die's links wend their way to the IO die or to other clients as well.

 

Assuming the die size measures above, and that it is as dense as the L3 of Zeppelin (including the sizes of tag arrays), the die composing of only cache would be ~160MB. 128MB seems reasonable, given inefficiencies and the space needed by IO and presumed directory entries (for dual socket coherency).

That's actually quite a bit less than I expected.

Another hypothesis is power. You want the main power and ground lines to go straight through to the chip, and the socket is designed for Zeppelins to be where those chiplets were placed.

 

29% IPC gain over Zen 1 in DKERN RSA+.

https://www.amd.com/en/press-releas...ance-datacenter-computing-to-the-next-horizon

And based on this, Zen 2 is around 70-80mm^2. That’s no memory controller, but it does include PCIe. That’s pretty good news for next gen.

 

I found it quite interesting that they're touting performance of 7.4TF FP64, 14.8TF FP32, 29.5 FP16, 59.5 INT8, and 118 INT4.

It puts AMD very close to RTRT hardware by the end of this year.

Am I right in thinking that some BVH accelerating hardware would take up little of the M160's 331mm2 die, but would put it in the same realm as the RTX2070 and 2080?

If so, I'm very much coming round to the idea of RTRT in the next gen consoles. I'd still like a two tier launch, and at this rate, it looks like even a low tier option could be looking at some 8-10TF of RTRT capable hardware.

The 6TF X1X renders Red Dead Redemption 2 at native 4K. Imagine what it would look like with an additional 4TF of RTRT and ML hardware taking care of all of the shadows, upscaling, and AA. Maybe reflections too, if that's not too costly.

 

Could someone give me more insight?

I've seen many negative comments in Anand saying the new product is 50% more dense but only 20% better in performance?

 

TF numbers alone are not enough to extrapolate performance between NVIDIA and AMD. NVIDIA has higher performance than their TF number would suggest. Because they compensate by having better polygon throughput, pixel filtrate, texturing and higher effective memory bandwidth. Also they have more advanced Tile Rendering than AMD.

 

1.25x performance for the same power. This is on TSMC, not AMD. Interconnect resistivity likely rearing its ugly head. Rumors were that Apple weren’t pleased either.

Wouldn’t this give atrocious latency?

 

I get that Nvidia's generally considered to be better, but AMD's going to provide the tech behind the PS5, for certain, and probably the XBoxTwo.

And if a late 2018, 7nm iteration of Vega can be used for ML, their hardware isn't that far away from being comparable in RTRT aptitude.

So my point isn't that AMD are going to come along with the best RTRT solution, just that it's promising that they're already so close to having one. It bodes well for industry support and inclusion in at least one of the PS5 and XBoxTwo.