Fewer memory chips and an easier layout of the package and the board save costs.
What about the space saved by easier ROP setup? I.E. no Crossbar...
Fewer memory chips and an easier layout of the package and the board save costs.
What does that even mean?
Was 2 at launch:Tahiti is "quad engine".
What does that even mean?
4 raster engines (+100% over R1000/Tahiti)
Probably depends on what engine you are talking about.Tahiti is "quad engine".
So you meant shader engines. And isn't Pitcairn Pro not also using just 16 CUs?Depends on what you term as engines - that's talking about geometry engines. In terms or shader architecture, why do you think Tahiti scales SKU's in 4 CU increments vs 2 in other products? The architecture is scalable in multiple vectors.
Yes, forgot, Pitcairn is the same org as Tahiti. Verde and Bonaire are 2.So you meant shader engines. And isn't Pitcairn Pro not also using just 16 CUs?
Which is kind of strange as we were told, that Pitcairn uses 6 CU groups (2 x 4 CUs + 4 x 3 CUs). How is that split? Or can CUs from the same group belong to different shader engines?Yes, forgot, Pitcairn is the same org as Tahiti. Verde and Bonaire are 2.
Pitcairn has 4 CU groups as has Tahiti.Which is kind of strange as we were told, that Pitcairn uses 6 CU groups (2 x 4 CUs + 4 x 3 CUs). How is that split? Or can CUs from the same group belong to different shader engines?
You mean shader engines as Dave and me just agreed .Pitcairn has 4 CU groups as has Tahiti.
I only used the terminology you used above. Pitcairn and Tahiti have 4 shader arrays (GCN parlance).You mean shader engines .
With the CU groups I meant the groups of CUs sharing the scalar L1 (kcache for some of the graphics guys) and instruction cache.
Actually, Dave called this engines (and some docs I looked into, too). I didn't use the word "array" at all. I always assumed array means all the CUs together (that's how it was named in the last documentation I looked into).I only used the terminology you used above. Pitcairn and Tahiti have 4 shader arrays (GCN parlance).
I was editing my post above with this possibility while you wrote that. But yes, that clarifies things. Thanks for that. It means the information given out during the CV and Pitcairn launches were maybe not fully correct, but now everything makes sense again.Pitcairn's organization of CUs within each shader array is a bit more complex because there are 5 CUs within each shader array. Within each shader array, 3 CUs share an I$ and K$ and the remaining 2 CUs share an I$ and K$. Each CU has its own L1$ and LDS.
Cape Verde has the same arrangement of Pitcairn except it only has 2 shader arrays.
Hopefully this clarifies things. If this information is not in the OpenCL Programmer's Guide (it should be), I'll make sure it's updated.
How often comes this up? That 3DCenter stuff is no leak, it's just a speculation.
They also claim 4.9Bil transistors and 64 ROPs.Some tech sites are still insisting on the 512-bit MI on Hawaii
AMD Hawaii will have a 512-bit memory bus
They also claim 4.9Bil transistors and 64 ROPs.