AMD Vega 10, Vega 11, Vega 12 and Vega 20 Rumors and Discussion

Discussion in 'Architecture and Products' started by ToTTenTranz, Sep 20, 2016.

  1. Malo

    Malo Yak Mechanicum
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    Going off-topic, does Mickey Mouse enter public domain in 2023?
     
  2. Grall

    Grall Invisible Member
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    In Sweden, we have the equivalent of design patents, but it's not called a patent. There's undoubtedly other differences as well of course, like any two similar laws would tend to differ between nations... :)

    One particular weakness with the U.S. patent system seems to be the ability to perpetually extend patent protection by either re-filing the original patent with changes, or filing a new patent with the original patent wording included - I'm not entirely sure which strategy is being used. Maybe both, IANAPL. :D

    Like for instance, this is how Intel is still having control over the x86 architecture, 40 fucking years after its creation.
     
  3. Anarchist4000

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    That diagram looks more or less like a 2S Epyc fully scaled out. Current designs feature 128M of cache and it's not inconceivable the 7nm Epycs could double that. That configuration is 8x16 PCIe lanes in theory all working as Infinity Fabric for added bandwidth. I don't believe there is an interconnect chip, but actual CPUs serving that functionality. That would provide direct access to system memory for the GPUs which is the design goal with HBM/HBCC serving as a LLC for each GPU.

    What will be curious to see is if they embed all the CPUs and GPUs onto a single board similar to what the exascale design demonstrates.
     
  4. 3dilettante

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    The chiplet concept in that concept paper differs from the implementation of Summit Ridge. A chiplet in that case is a silicon chip that cannot function independently of an active interposer underneath it. The various Zen products are composed of one or more x86 SoCs that are fully capable of working on their own and interfacing with the system.
    The HPC concept has CPU and GPU chips that are stripped of a significant amount of ancillary functionality that either goes into neighboring chips/chiplets or is handled by the IO and memory network hosted on the active interposer they are placed on.

    I am not sure that there is an upside to having a single central chip hosting the IO and memory interfaces. This would rob AMD's architecture of a key part of its scalability by no longer scaling memory and IO with the area and perimeter of the x86 chips, and instead leaving the central chip's fraction of the total area and perimeter as the upper limit. If it is a separate chip on the package, its perimeter is doing double-duty by hosting more memory and IO than can be fit on a single chip and then the necessary interconnect to allow it to communicate with the x86 chips. The HPC APU concept uses stacking to keep a lot of that connectivity from taking up chip perimeter.

    Some of AMD's other recent patents are about MCM packaging and interconnects through a more standard substrate, which points to some possible tension in AMD's future direction versus its relatively far-off Exascale projections, or an indication that the next step in EPYC is an incrementally denser MCM package.

    While I don't know how many different land mines there are, a good chunk of Intel's continued control is based on performant implementation of its instructions, and generally the modern ones. If an implementation went back 20 years in ISA terms, it might be more clear legally. Whether there's a point to such a thing is less clear.

    The vendors patent a good swath of what they do, and even if some of the more modern IP pool might not stand up to legal challenge, it would involve a legal fight and confidence that said patent doesn't have 99 friends to catch you--hence the number of cross-licensing agreements. Perhaps some of Intel's motivation for the many ISA revisions and extensions is to keep line of full compatibility covered with patents.

    AMD's continued role in modern x86 is also unclear, since its coup with x86-64 is nearing the end of its coverage period. Speaking of coverage, another item I am not clear on is what AMD can or will do going forward. The most recent cross-licensing agreement I am aware set an end to the coverage period that appears to end around Zen or the start of the design phase of the next core.
     
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  5. CSI PC

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    I would say the closest example would be Power8 and more relevant now Power9 with the on-chip fabric switch and the L3 cache/memory/IO and scaling up/out with SMP.
     
  6. Digidi

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    #5246 Digidi, Apr 20, 2018
    Last edited: Apr 20, 2018
  7. Malo

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  8. Digidi

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    It is interesting because AMD stated that they can't include primitive shaders to the driver, but they can help developers to make culling over shaders. AMD said also it would be similar to primitive shaders.

    Reading this patent looks like primitive shaders is nothing else than normal shaders used for culling automatically.
     
  9. silent_guy

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    It needs to be “reduced to practice.”

    However, that act of writing it down in a patent counts as being reduced to practice.

    So... no.

    (Usual IANAL disclaimer, but that’s what a lawyer told me.)
     
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  10. rwolf

    rwolf Rock Star
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  11. eastmen

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  12. Pressure

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    It's the Radeon Instinct MI25, so unless you have deep pockets ;)
     
  13. eastmen

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    I do …. they are just empty :oops:
     
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  14. ToTTenTranz

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    The tweet in question:




    The Instinct MI25 uses Vega 10, the same GF 14LPP chip as Vega 64/56, Vega FE, etc.

    The card announced here is the 7nm Vega 20 with 4x HBM2 stacks and half-rate FP64.


    Also, there's a good chance Vega 20 is being made at TSMC, since they're the ones ramping up 7nm for volume production.

     
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  15. Kaotik

    Kaotik Drunk Member
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    I'm sure he just meant it's same series as MI25 / replacement for MI25, aka Radeon Instinct top-of-the-line

    I would call this confirmation that the first samples are from TSMC (edit: even if I realize that she didn't outright spell it out literally)
     
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  16. Esrever

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    It makes sense to use TSMC for the first parts flagship parts, most people expect Globalfounderies to be about half a year behind TSMC for 7nm. If TSMC can allow for a 2019Q1 launch, then we will probably have to wait till Q3 for the Glofo parts to launch.
     
  17. Cat Merc

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    So AdoredTV claims that he has a source stating there will be dual and triple Vega 7nm cards, and they will use some sort of infinity fabric based interconnect to avoid crossfire.

    Rumor is a rumor, but the thought intrigued me.
     
  18. 3dilettante

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    The earlier slide leaks had Vega 20 featuring xGMI, which is the fabric's protocol extended to run over PCIe interfaces. That's what EPYC does for its dual-socket systems, though how this gets used for GPUs depends on implementation details that have not been leaked.
     
  19. Cat Merc

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    EPYC actually uses GMI rather than xGMI, so it will probably be different in the details.
     
  20. Samwell

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    Thanks for confirmation, that there will be no dual and tripple Vega. :grin: I don't believe that adoredtv has any sources, more that whatever this guy mentions won't happen.
     
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