Maybe AMD is seeding LinkedIn with fake profiles to throw off the competition.
Earlier discussions tried to sort out the usage of each entry:
https://forum.beyond3d.com/threads/...peculation-rumors-and-discussion.56719/page-9
There seem to be some tweaks, but it's going back to a minor bump in version from Tonga for everything but multimedia. Is DCE related to compute? That seems to be inherited from Carrizo. (edit: Or is it the display controller?)
The lack of a *new* tag on things like the rasterizer and color blocks could be what is housed under the GFX label.
When looking at the IP levels, there seem to be increases for quite a bit of blocks.
So it really depends what the gfx IP level covers. If it's just the shader core and not things like ROPs and other essential blocks that are not part of the shaders, then they could still add those feature levels while keeping the shaders identical.
There definitely are changes in their codecs. So that concern is probably covered as well.
Ok, thanks for clarifying.The GFX block is big - command processors, graphics & compute pipelines, shader core/ISA, CBs/DB (ROPs)... I think texture cache/filtering is in there too but not sure ATM.
It better be. Though a new architecture will hopefully also fix the current clock deficit of GCN.Perhaps 4096 ALUs is the little Vega.
So, ahem, AMD seems to be making mainstream and performance GPUs based upon Polaris that cut down ALUs, just in time for async compute games to come along and demand more compute
Perhaps 4096 ALUs is the little Vega.
If it's a "new, efficient" architecture, perhaps we're talking extreme ALUs. Sorry, old old joke.
Maxwell v1
Maxwell v2 -- HDMI 2.0, FL12_1
GCN Gen3
GCN Gen4 -- HDMI 2.0a, DP 1.2 and FL12_1?
DP 1.3 you mean? They're already 1.2aMaxwell v1
Maxwell v2 -- HDMI 2.0, FL12_1
GCN Gen3
GCN Gen4 -- HDMI 2.0a, DP 1.2 and FL12_1?
Ooops, sorry for the typo. I mean DP1.3.DP 1.3 .. DP 1.2 is so last year. and a bit more in term of connectivity as required for full HDR supportt .
ANOTHER Linkdin leak? http://wccftech.com/amd-vega-10-4096-stream-processors/
Either AMD has been totally negligent in its NDA agreements and checking for leaks, or these are somehow fake? Either way it's odd for so many "leaks" from the same source to happen in a row, let alone for so many people in a row to make the same mistake of putting assumedly NDAd specifics of chips not out yet on their resume. Oh yes, "let's show that we happily break NDA stuff on our resume, via our resume! This is surely a good way to get hired."
But hell, who knows. Maybe it's true, all of it *Han Solo face.
I think somewhere along the line AMD talked about instruction caching having an effect on IPC.Well they did mention their IPC is going to better for Polaris, I would think that would be the same for Vega, so maybe 4096 is what they went for?
Where did you hear this? I'd like to read about it. Also why doesn't AMD just fix the compiler?The register file is simply too small for complex shaders given the current way GCN works and the stupidity of the compiler which always maximises register allocation in favour of issuing less instructions.