All we know about HBM is that Hynix and AMD partnered to get the first version to market.
Concluding that this somehow contractually ties AMD to Hynix for the foreseeable future is a bit of a big step to make IMO.
AMD: Speculation, Rumors, and Discussion (Archive)
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Concluding that this somehow contractually ties AMD to Hynix for the foreseeable future is a bit of a big step to make IMO.
Tonga was launched in September of 2014 as the 285. This seems closest, particularly if we give Polaris a roughly mid-year launch, fixing the year numbers as being New Years of each year. It's not quite the same starting point for extrapolation than if more recent chips were used, as Tonga failed to distinguish itself from prior and then-contemporary cards.
It might be worthwhile comparing chips on 28nm with similar power levels to guess where Nvidia might end up relative to Polaris.
You are aware of the rumour/news that AMD tied up HBM1 memory from Hynix?
So it does suggest there is some kind of contract, in same way AMD still has that contract for X amount of silicon from Global Foundries.
Not really a big step, when one considers contractual obligations and how companies tie themselves for several years, especially if they initially have priority on a product as AMD did/does with Hynix, along with the fact AMD shows first HBM2 in 2017 and comment that they will not implement HBM2 until it is mainstream (seems it will take at least a quarter longer for Hynix to enter same level of mass production as Samsung).
Cheers
As a counterpoint, AMD has scrapped memory plans before when it couldn't get a second source. Kaveri could have used GDDR5M if one of the manufacturers didn't go under.
Purposefully locking into a single source for memory runs counter to that, and I'm not sure what looks worse: if HBM1 has only Fury at present as a consumer, if a limited product like Fury can capture all of HBM1's volume, or if AMD is buying single-sourced DRAM in excess of Fury's needs.
That's specific to the creation of GF. There was no way that the buyers for AMD's fabs were going to assume so much liability and expense and then let AMD waltz off. It seems almost a given that AMD would have done better if it had more freedom to avoid GF's blunders.
Hynix and AMD don't have that kind of financial stand-off built into their relationship.
I'm aware of these rumors, but I don't think they're very irrelevant. An exclusivity contract between to parties is pointless if it has no monetary value. It's like George Constanza asking for a prenup. It's doubtful that Nvidia would have designed a 28nm chip without such an exclusivity contract, since HBM's performance was a bit of a mismatch in terms of what could be done with it. (I expect HBM2 to be similarly mismatched, TBH.)
AMD knew that HBM would be a JEDEC standard and the Nvidia would use it as well. It makes little sense to tie yourself to a single supplier when others are expected to join in.
I think AMD simply aligned its product roadmap with Hynix and that Samsung happened to be earlier. It's probably not a big deal: Nvidia can easily eat the higher initial cost of HBM2 with its compute product line, something where AMD doesn't have a lot to lose.
It would be nice to know if AMD is using Tonga as its 28nm baseline.
It might help in handicapping what to expect from the 2.5x power efficiency gain, which earlier in this thread was discussed as a 70/30 split between process and architecture.
I tried to find an architecture that has a power range at the 285/380 level, and it lead to me to this initial comparison:
http://www.anandtech.com/bench/product/1592?vs=1442
Any immediate objections to the choice?
It might help in handicapping what to expect from the 2.5x power efficiency gain, which earlier in this thread was discussed as a 70/30 split between process and architecture.
I tried to find an architecture that has a power range at the 285/380 level, and it lead to me to this initial comparison:
http://www.anandtech.com/bench/product/1592?vs=1442
Any immediate objections to the choice?
iMacmatician
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I'm trying to see if the x-axis gives any clues. The center of the Polaris square is 18 (and a half) months after the center of the 28 nm GPUs square, so if the start of each year corresponds to the center of each "201x," then Polaris corresponds to end of May / start of June 2016 and 28 nm GPUs corresponds to November 2014. That's probably more precision than is relevant for this roadmap, since the squares have to go somewhere after all. The desktop or FirePro card with a launch date closest to November 2014 that I could find (on Wikipedia) is the R9 285 (September 2014).
Of course, if the 28 nm GPUs square does not refer to one chip or GCN revision, then things may get more complicated.
Of course, if the 28 nm GPUs square does not refer to one chip or GCN revision, then things may get more complicated.
The Polaris block seems to represent product becoming available. No other event related to it seems to work as an interpretation, and as a tentative roadmap it works that way for Vega and Navi.
Perhaps the starting point is AMD sandbagging, but if it's not Tonga then the 28nm block becomes unmoored and creating an amalgam of implementations doesn't necessarily create a better reference point.
Perhaps the starting point is AMD sandbagging, but if it's not Tonga then the 28nm block becomes unmoored and creating an amalgam of implementations doesn't necessarily create a better reference point.
Maybe you can use power figures that measure gfx cards only not the whole PC. It will be difficult to compensate for the additional power consumed by the CPU when doubling the fps.
Reviews tend to not think about Tonga when reviewing the 980, and in the reverse. The card that gets significantly higher FPS being hobbled by a CPU that draws more power tends to weigh the comparison in a manner more complementary to Tonga than not.
Was it ever proved/disproved the news-rumours regarding AMD having priority/supply agreement for HBM2 with Hynix?
This came out in 2015, but they also commented there would be no HBM2 in 2016 according to their "source" in AMD and that was reported quite awhile before the current slides.
Just asking as it may had been just one of those made up rumours, although they seem to be right about HBM2 now.
I just do not know if all of these were triggered by WCCF, which is not ideal
Cheers
I made this earlier for a project I'm working on
http://i.imgur.com/YiIzlWf.jpg
So Tonga as 1x, Polaris as 2.5x Tonga, Vega is November 2016-January 2017 by my assumption.
HBM1 for Polaris 10 is a really interesting point but I don't think so. I hope so though, that could really put the cat amongst the pigeons with Polaris 10 nearing 980 Ti performance I believe.
http://i.imgur.com/YiIzlWf.jpg
So Tonga as 1x, Polaris as 2.5x Tonga, Vega is November 2016-January 2017 by my assumption.
HBM1 for Polaris 10 is a really interesting point but I don't think so. I hope so though, that could really put the cat amongst the pigeons with Polaris 10 nearing 980 Ti performance I believe.
Anyone know what the relevance is for 28nm near 2015 for that chart? http://i.imgur.com/YiIzlWf.jpg
Tonga 285 came out Q3 2014.
Tonga 380 came out half way through 2015.
And the other cards came out earlier than Tonga.
They ignoring all other architectures?
Cheers
Tonga 285 came out Q3 2014.
Tonga 380 came out half way through 2015.
And the other cards came out earlier than Tonga.
They ignoring all other architectures?
Cheers
Tonga was
Q3 2014 would be very close close to the start of the box near 2015. It would also be the last arch with GDDR5 rather than HBM1. For me this is what makes most sense for AMD's 2.5x perf/Watt.
Q3 2014 would be very close close to the start of the box near 2015. It would also be the last arch with GDDR5 rather than HBM1. For me this is what makes most sense for AMD's 2.5x perf/Watt.
I don't recall what was being claimed or what version of HBM it applied to, and I have not run across much either way.
Having some kind of additional benefit/arrangement as a result of working with Hynix seems plausible, but how that aligns with what was being claimed, or what kind of impact that could really have on Nvidia or anyone hasn't come up.
So far, it doesn't seem like getting early dibs on HBM has had major import if it is true.
A slide posted by CarstenS a while ago suggests that Nvidia are a little worried about HBM2 power levels going forward. If AMD has gained anything from their HBM leadership, this could be a good candidate, especially as Vega appears to have further increased perf/Watt over Polaris.
Did you mean this post?
HBM takes the interface power draw way down, leaving the power cost of bank and row activation as the dominant component.
For a given amount of data being accessed per activation, raising bandwidth inevitably means more DRAM arrays being hit, regardless of how improved the interface power is. HBM2 actually makes the interface power slightly worse, since it is driving HBM's interface harder. Pseudo channel mode and its effectively smaller activation cost may explain why activation power didn't double with HBM2 compared to what HBM would have required if forced to the same bandwidth.
If GDDR5 were forced to the data rates in question, the array power cost would be very large if we could somehow discount the prohibitive interface power consumption.
That's a DRAM problem for the projected high bandwidths wanted in the future. HBM2 could halve the device count and beat HBM.
HBM takes the interface power draw way down, leaving the power cost of bank and row activation as the dominant component.
For a given amount of data being accessed per activation, raising bandwidth inevitably means more DRAM arrays being hit, regardless of how improved the interface power is. HBM2 actually makes the interface power slightly worse, since it is driving HBM's interface harder. Pseudo channel mode and its effectively smaller activation cost may explain why activation power didn't double with HBM2 compared to what HBM would have required if forced to the same bandwidth.
If GDDR5 were forced to the data rates in question, the array power cost would be very large if we could somehow discount the prohibitive interface power consumption.
That's a DRAM problem for the projected high bandwidths wanted in the future. HBM2 could halve the device count and beat HBM.
Yes that post, thanks.
Could there be an effect that Nvidia is suffering here due to being "late" to HBM. Wasn't there a similar situation with GDDR5 at first as well, outside of the actual interface?
I wonder if AMD/SK´s close relationship over many years, if this wasn't seen and worked around already. I'm really just going on what the roadmap says about Vega and what Nvidia says about HBM2 in their presentation though.
Could there be an effect that Nvidia is suffering here due to being "late" to HBM. Wasn't there a similar situation with GDDR5 at first as well, outside of the actual interface?
I wonder if AMD/SK´s close relationship over many years, if this wasn't seen and worked around already. I'm really just going on what the roadmap says about Vega and what Nvidia says about HBM2 in their presentation though.
Row power and column power are inside the DRAM and would be something anything on the other side of the interface has to live with.
The slide does not cover the GPU or controller's contribution, which if all else is equal with the DRAMs should mean accesses will require the same power.
AMD and Nvidia cards have treated the GDDR5 devices themselves in pretty consistently, leaving them bare or adding a thermal pad or heatsink in equal measure.
The future may need to do something about how memory is structured--which that slide seems to hint at, or the arrays need to be accessed less (i.e. do not require that much bandwidth).
The slide does not cover the GPU or controller's contribution, which if all else is equal with the DRAMs should mean accesses will require the same power.
AMD and Nvidia cards have treated the GDDR5 devices themselves in pretty consistently, leaving them bare or adding a thermal pad or heatsink in equal measure.
The future may need to do something about how memory is structured--which that slide seems to hint at, or the arrays need to be accessed less (i.e. do not require that much bandwidth).
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