Since they are introducing a new SOC interconnect and how long their die stacking program has been running, I guess they would have been aware of the extensibility.
It would depend on whether AMD could treat the off-die links and the physical/electrical discontinuity introduced by the microbumps more like neighboring blocks on the same die or more like chips on an MCM.
The power/bit cost of data movement on die is still better than going off-die with an interposer. HBM is not 10x or more efficient than the DRAM it replaces, so the prospect of taking traffic that was once faster and more efficient and making it as efficient as HBM may constrain the unspecified performance upside to doing this.
I'm not sure if going this route implies a step back from the long-predicted convergence of the architectures, as their differences would be enshrined by distance once again.
For GPUs, if the GPU can make use of HBM, the cost is always there and a "normal" version is off the table. For CPUs, that's my question too - say if they would still give the single die part an interposer, make another non-interposer version, or use flip-chip bumps directly (but still 2.5D, so mixed bump size for the interposer...).
Perhaps if AMD actually doubled down on this, there would only be 2.5D chips with HBM links to a PHY driver component for off-interposer connectivity.
The interposer does present a set of coarse metal layers, which AMD is actually losing by going to generic foundry processes. Perhaps if it optimized towards this reality, something could be done to mate the chips more closely than the comparatively coarse microbumps we have now, and maybe some of the passive components or non-digital silicon could be moved onto or into the interposer, freeing up the primary die for other things.
I think there were some presentations for alternative schemes, I think Tezzaron presented something like using tungsten vias thanks to extreme die thinning. Whether that is better or can be worked economically for this, is a fair set of questions.
GPU in that range is often a really huge die... Anyway, one bullet point of 2.5D is to break down monolithic SOCs, and since the GPU is likely getting HBM, it seems a broken-up one is fairly natural move.
The 270X is a little below 200W, and Tahiti is 250W+.
Somewhere between 212mm2 and 360mm2 is the minimum footprint a chip made by AMD can break 200W with a monolithic ASIC.
This is assuming that there is a physical barrier like insufficient pad area for the required number of power pins, and that the 270X is a reasonable example of AMD's minimum.
