Could you explain that assertion.
AMD: Southern Islands (7*** series) Speculation/ Rumour Thread
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Could you explain that assertion.
A CU is expected to much more denser than an SM.
A big feature that is being overlooked is coherency. It seems AMD will be offering full coherency while NV only offers semi coherent L1.
There will be a DX11.1 or 12.
So far:
Modularity - graphics and compute hardware are decoupled.
Parallelism - concurrent kernels from multiple application contexts.
Not sure how that relates to what I stated.
Yep, and it looks like they have an option to disable full coherency too. The GLC bit.
Oh, I haven't heard a peep about either.
I think the compute core and the ff hw was decoupled earlier as well. What has changed in this context?
Cayman can do 2 kernels simultaneously.
I'd expect noise about that ~12 months before xb720.
A CU can now do 4 threads from 4 different apps as well. I may have not grasped the idea fully, or correctly, but does any one else see a point in bunching different threads in to a CU? IMHO, MIMD over CU's would have been better than MIMD within a CU.
For a start, you can kiss your L1 goodbye, as each will get just 4K on average?
For a start, you can kiss your L1 goodbye, as each will get just 4K on average?
How is that supposed to work with just 16 L/S units?
16*4=64
Unless you are not referring to the clock those units run at (hot clock), of course.
The cost of giving up VLIW ... and such a nasty cost it is.
That is what I meant.
We (well, at least me) referred to a SM with a peak rate of 32 fma/clock. That clock is then of course the hot clock.
Fermi-SM: 64 Bytes/hot clock aggregate bandwidth, 32 fma/ hot clock (or 48 fma/hot clock)
AMDs CU: 64 Byte/clock from cache/memory, 128 Byte/clock from LDS, 64 fma/clock
Just because it can be done, doesn't mean it needs to be or even will be done at all as default behaviour.
The L1/LDS combo in Fermi runs at the base clock.
That does not matter for the flops/bandwidth question. One just has to use the same clock for flops/cycle and bandwidth/cycle that the division makes sense. If you take the base clock, the Fermi-SM would do 64 fma/cycle, the ratio does not change.
What's changed is that they've caught up to Fermi in several important areas and those advantages actually matter now (and have been further generalized). Also texture units were coupled to a SIMD in Cayman, that's no longer the case.
Yes the ratio doesn't change but normalizing to base clock makes the comparison to AMD's architecture easier. Scheduling, instruction issue, operand fetch, caches all run at base clock on Fermi and halving the throughput of those processes based on the ALU clock is just confusing/misleading.
flops/clock and bandwidth/clock comparisons are easier when you're talking about similar clock speeds no?
I can't see any reason why they will crow about it if they weren't planning to implement it and I can't see why they would implement it if they didn't want to use it quite a bit.
The texture units (still a quad TMU, probably modified) are an integral part of the L1 cache block as can be seen here:
It was also mentioned explicitly in the talk about the fusion system architecture that there is the usual filtering hardware in there.
So the comparison at Fermi's base clock:flops/clock and bandwidth/clock comparisons are easier when you're talking about similar clock speeds no?
nvidia SM: 128 byte/cycle aggregate bandwidth, 64 fma/cycle (96 for GF104 type SM)
AMD CU: 64 byte/cycle cache/memory + 128 byte/cycle LDS bandwidth, 64 fma/cycle
I don't remember TMU organization being discussed. My guess is that TMU's are still coupled to a CU.
I wasn't saying they aren't there. Just that the SIMDs can be scaled independently of TMUs now. See my earlier posts in this thread regarding AMD's ALU:TEX ratio.
Yeah.
Yeah to a CU, not to a SIMD.
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