Based on all that they have spoken of the L3 cache, and all the leaks, I think that the Infinity Cache consists of 16 slices of 8MB with a 512b interface on each of them. The easiest, most sensible method of varying it's size is to increase/decrease the amount of those slices. As the driver will definitely need to know the amount of cache on the card, I think it's a good guess that they would include this as a new property in the drivers. Looking at the
mac os driver properties, there are 3 new ones.
unknown2 seems to be the total CU count, and
unknown0 doesn't fit, but
unknown1 is 16 on Navi 21, which is exactly right.
Based on entirely this, I predict that the 40-cu Navi 22 will have 96MB of infinity cache, that the 32-cu Navi 23 will have 64MB, and that the upcoming APUs will both have 32MB.
The APUs sound about right, assuming they are targeting 1080p gaming (framebuffers scale linearly with resolution, and 1080p is 1/4th of 4k). The middle chips are a bit weird. They definitely can't do 4k (not just because lack of cache, but also compute power), but if you are targeting 2560x1440, you don't really even need 64MB. Maybe the amount of slices is high for the bandwidth, not for the cache amount?