AMD: R9xx Speculation

[no-X]

I'd rather have $250 card that performs well on single card, single chip mode than $280 card that's equally fast on single chip...

Me too, but since when boosts 1.5mm² of silicon GPU's price by $30?

 

[hkultala]

Me too, but since when boosts 1.5mm² of silicon GPU's price by $30?

Might make much more in practice. IO pins need their padding etc.

But maybe the $30 as a bit too much.

 

[no-X]

250mm² of RV770 was enough for side-port padding. 330mm² of RV870 should suffice.

Anyway, it might be 2.5mm² difference, but the difference in manufacturing cost would dissolve in current selling price...

 

[rpg.314]

250mm² of RV770 was enough for side-port padding. 330mm² of RV870 should suffice.

Read Anand's piece on the cypress backstory. 330mm2 wasn't enough for sideport in cypress.

 

[Jawed]

AMD, ATI have not used any non-power-of 2-memory bus widths EVER on any chip, so I consider it quite unlikely they would do it in "R900" either.

Let's hope there are some serious uncore changes...

And side-port.. that's waste of pins and die size for the >98% of cases where we have only single chip. I'd rather have $250 card that performs well on single card, single chip mode than $280 card that's equally fast on single chip mode but gives slightly better scaling IF paired with another chip/card

It seems the sideport was deleted from Cypress and the Anandtech RV870 Story article implies it will make a comeback:

Sideport was Carrell Killebrew’s favorite feature, and he had to give it up.

In early 2008 ATI realized they had to cut this chip down from 20 - 22mm on a side to 18mm, everyone had to give up something. Carrell was the big advocate for making 870 smaller, he couldn’t be a hypocrite and not give anything up.

A bunch of my conversation with Carrell at this point had to go off the record. Sideport would have been useful in RV870, but it’s unfortunately not there. Although he did tell me not to be surprised if I saw Sideport again at some point. Carrell doesn’t give up easily.

http://v3.espacenet.com/publication...T=D&date=20100408&CC=US&NR=2010088453A1&KC=A1

For example, the cost of bridge integrated circuits (ICs) is relatively high. In addition, the size of a typical bridge IC is comparable to the size of a graphics processing unit (GPU) which requires additional printed circuit board area and could add to layer counts. Bridge ICs also require additional surrounding components for power, straps, clock and possibly read only memory (ROM).

Describes a logical sideport which can be implemented without any dedicated physical lines. Instead each chip uses half of its 16 PCI Express lanes to talk to the CPU and the other half to talk to the other GPU.

This architecture requires that all traffic from CPU to GPU(s) is seen by both GPUs concurrently across the 16 lanes. The two GPUs then forward-data to the other when it's known that the data arriving on their set of 8 lanes wasn't destined locally, but remotely.

Alternatively a ring is formed by 2 or more GPUs' forwarding messages in one direction.

So, in theory, no need for a physical sideport.

 

[no-X]

Read Anand's piece on the cypress backstory. 330mm2 wasn't enough for sideport in cypress.

They removed sideport to save die-size, not because the die would be too small to fit the pads. At least I understand it that way.

 

[rpg.314]

My understanding is that the pad size grew, so there wasn't much space left for sideport's pads.

 

[TKK]

New rumor about SI parts: First SI part to be released will be Bart in mid-October (though they might have misspelled it, they also called Cayman "Cayment").

Bart(s) is supposed to be pin-compatible with Cypress, which would indicate a 256-bit memory interface and a rather large die for a Juniper replacement. Performance "between 5770 and 5870", TDP over 150W (2x6pin), at least for Bart(s) XT. My guess would be something like ~1280SP/64TMU/32ROP @750+ MHz core and 1+GHz memory, because with that kind of power consumption it needs to approximately match the 5850 or at least GTX460-1GB to make sense.

Cayman/Cayment launch will be late October or November, 1GB 6Gbps GDDR5, 6pin+8pin, so it's at least very close to or even above 225W.

 

[rpg.314]

May be the translation is borked, but I didn't see any pin compatibility bit there.

 

[no-X]

"Zudem ist der Chip des "Bart" Pinkomaptibel mit dem PCB der HD5800..."

 

[neliz]

Latest?

LoooooooooooooooooooooooooooL

Also, everyone knows the correct names of the islands, the wrong spelling is just to make obvious cat obvious.

and this one from may:

 

[Kaotik]

Latest?

LoooooooooooooooooooooooooooL

Also, everyone knows the correct names of the islands, the wrong spelling is just to make obvious cat obvious.

and this one from may:

I call fake just due the 384bit bus on 2 chips if nothing else

 

[neliz]

I call fake just due the 384bit bus on 2 chips if nothing else

It's a Question mark, why would they release the specs 5 months in advance?

Ah well, it might be here sooner than we think, we'll see.

 

[Bouncing Zabaglione Bros.]

I hope AMD have managed to pull a high end refresh back into 2010. Early next year is a bit late given Nvidia are beginning to pull themselves together and force prices down. 460 pricing and performance is putting pressure on the 5850, and a fixed 480 with a lower price will do the same to 5870 (if Nvidia get it out for Q3 as predicted).

 

[neliz]

I hope AMD have managed to pull a high end refresh back into 2010. Early next year is a bit late given Nvidia are beginning to pull themselves together and force prices down. 460 pricing and performance is putting pressure on the 5850, and a fixed 480 with a lower price will do the same to 5870 (if Nvidia get it out for Q3 as predicted).

What's the main reason (for nv) to lower the prices and why isn't AMD doing it?

 

[trinibwoy]

What's the main reason (for nv) to lower the prices and why isn't AMD doing it?

Nvidia is defending their quickly eroding market share and AMD needs all the cash they can get. It's not really that complicated

 

[racca]

My understanding is that the pad size grew, so there wasn't much space left for sideport's pads.

No, he said it would be hypocrite not giving up anything.
That's called compromise not necessity. Ergo, it's more than likely it will fit in nicely.

Besides it's very hard to believe with more than 10% space to pad (that's roughly 32 bits more), they can't get an already present I/O to fit this time.

 

[jaredpace]

Could anyone guess the stream processor count or mem. bus width for Barts XT & Cayman?
Cayman < 300w, 6gbps, 1920SP 256bit
Cayman < 300w, 6gbps, 1920SP 384bit
Cayman < 300w, 6gbps, 1920SP 512bit,
Barts ~150w, 5gbps, 960SP 256bit
Barts ~150w, 5gpbs, 1280SP 256bit

-or something completely different

Perhaps 1920/384 for Cayman and 1280/256 for Barts. And I guess Antilles is an underclocked & undervolted 2xCayman board. And Eyefinity 4 "+" seems cool. 5 display outputs on a single card... wow. Hopefully we wont be required to use one of the miniDP's for our 3rd display.

 

[Kaotik]

The high end single chip should be around same TDP as Cypress at max

As for Eyefinity improvements, I'd guess the biggest difference will be either fitting one more TMDS transmitter (to enable that 3 displays with dvi/hdmi), or then do what some AIB is already planning to do on HD5-series - enable 3 displays on DVI as long as the resolution of each display is something you can push out a single-link DVI

 

[neliz]

As for Eyefinity improvements, I'd guess the biggest difference will be either fitting one more TMDS transmitter (to enable that 3 displays with dvi/hdmi), or then do what some AIB is already planning to do on HD5-series - enable 3 displays on DVI as long as the resolution of each display is something you can push out a single-link DVI

The Eyefinity improvement will be the removal of the current requirement to run Eyefinity in anything over 1920x1080.