AMD: R9xx Speculation

[rpg.314]

What about the side port?

We had first generation sideport RV770.

Second generation sideport was scrapped, but obviously development continued even if the current chips don't feature it.

Third generation side port? What would that be able to do?

I have no idea if side port can fix it. But i/o pins are expensive as they are relatively scarce on smaller dies.

 

[Squilliam]

I have no idea if side port can fix it. But i/o pins are expensive as they are relatively scarce on smaller dies.

Well they are expensive, but given the short distance between the two dies they could potentially have a lot of throughput and relatively low latency on only a small number of pins.

Realistically how much data would have to be shared in order to make a pair of GPUs perform close to how a single larger die would?

 

[rpg.314]

Well they are expensive, but given the short distance between the two dies they could potentially have a lot of throughput and relatively low latency on only a small number of pins.

True, but another question is whether you'd be better off using those I/O pins for memory? Especially with memory bandwidth growth slowing/stalled.

Realistically how much data would have to be shared in order to make a pair of GPUs perform close to how a single larger die would?

Potentially, all the geometry data. And mind you it isn't small with all the tessellation.

 

[rpg.314]

http://www.phoronix.com/scan.php?page=article&item=amd_evergreen_3d&num=1

AMD's Radeon HD 6000 series whose GPU family codename is "Southern Islands" is launching later this year. Besides their open-source developers starting early on this Linux upbringing (their proprietary driver team still should have same-day Linux support), it's rumored that the ATI Radeon HD 6000 architectural changes aren't too significant, which should reduce the workload of the open-source developers by being able to build upon the existing DRM/Mesa/DDX code.

Better linux drivers, .

Is some ocl love on the table too, or not?

 

[GZ007]

Potentially, all the geometry data. And mind you it isn't small with all the tessellation.

And what if the two dies wouldnt be same . One would have rops, cache, memory controlers, IO and the second one rest (and maybe separated they could have smaler die are together if they would be clever placed ). The second die would be only conected to the first die and not the pcb. You dont need to share anything this way just lots of bandwith and low latency between the two.

 

[rpg.314]

And what if the two dies wouldnt be same . One would have rops, cache, memory controlers, IO and the second one rest (and maybe separated they could have smaler die are together if they would be clever placed ). The second die would be only conected to the first die and not the pcb. You dont need to share anything this way just lots of bandwith and low latency between the two.

Correct me if I am wrong, but what you just described, isn't it a fancy layout which does not enjoy the advantages of lower development costs? A bit like x360's gpu.

 

[trinibwoy]

You dont need to share anything this way just lots of bandwith and low latency between the two.

You will never be able to achieve the levels of on-die bandwidth and latency available today by connecting two separate die together.

 

[GZ007]

You will never be able to achieve the levels of on-die bandwidth and latency available today by connecting two separate die together.

The mind blowing xTB/s on-die bandwith is agregated bandwith of the cache-s thanks to the paralel rendering. The main idea was to not split the shader clusters and leave them on the second die.
Do you think that the xenos parent die has just 32GB/s on-die bandwith because the two dies
have only 32GB/s bandwith betwen them.

 

[trinibwoy]

The mind blowing xTB/s on-die bandwith is agregated bandwith of the cache-s thanks to the paralel rendering. The main idea was to not split the shader clusters and leave them on the second die.
Do you think that the xenos parent die has just 32GB/s on-die bandwith because the two dies
have only 32GB/s bandwith betwen them.

Uh what? There's 32GB/s between the dies but there's also 256GB/s between the ROPs and memory on the eDRAM die which only serves framebuffer operations. Texture, geometry and all other data is stored on regular old DDR3 connected directly to the main die. Your analogy doesn't work as Xenos is a highly customized setup not suited for the general workloads a desktop graphics card must handle.

In your design how are you planning to expose the full DDR bandwidth to the shader core and texture units?

 

[Squilliam]

True, but another question is whether you'd be better off using those I/O pins for memory? Especially with memory bandwidth growth slowing/stalled.

But don't you need something like 64 pins for a 32bit bus? 64 pins isn't going to make much difference, especially as ATI doesn't seem to use 96/192/384 bit bus widths.

Potentially, all the geometry data. And mind you it isn't small with all the tessellation.

Which would surely not be too excessive given the PCI-E isn't significant in comparison?

 

[hoom]

Could have sworn we went through this multi-die stuff both of the last two generations & it still hasn't happened

 

[Jawed]

Precisely. Maybe at some point they'll ditch the bridge chip.

 

[rpg.314]

But don't you need something like 64 pins for a 32bit bus? 64 pins isn't going to make much difference, especially as ATI doesn't seem to use 96/192/384 bit bus widths.

I don't think 64 pins come cheap, especially on juniper class die.

Which would surely not be too excessive given the PCI-E isn't significant in comparison?

Data is sent across pci-e once, but read from gpu ram many times. Even if upload-to-gpu is slow, it has less impact on performance than gpu bandwidth.

 

[Unknown Soldier]

ATI Preps New Dual-Chip Flagship Graphics Card - Rumours

ATI, graphics business unit of Advanced Micro Devices, will launch a new dual-chip graphics card by the end of the year, according to a rumour published by a China-language web-site. The card will replace the current top-of-the-line ATI Radeon HD 5970 graphics accelerator.

The forthcoming flagship graphics board will be powered by two chips featuring the yet unannounced Southern Islands architecture. The information indirectly implies that power consumption of the future graphics processing units (GPUs) will not be too high and will allow AMD's ATI unit to put two of such chips onto a single card without exceeding standard 300W power envelope, which is crucial for meeting requirements of large system builders. As reported previously, ATI Radeon HD 6000-series graphics boards will become available in late October or early November, 2010.

Not a lot is known about the Southern Islands family of products. The SI family will offer higher performance compared to currently available ATI Radeon HD 5000 “Evergreen” line, but will hardly be considerably more advanced in terms of feature-set. It is rumoured that designers of the new GPUs concentrated mostly on improving efficiency, but not on building something completely new from scratch, which is why certain building blocks of the new Sothern Islands family will be inherited from the current Evergreen line.

According to the report from Cnbeta web-site, ATI "Southern Islands" will also feature an improved version of ATI Eyefinity technology as well as a more advanced Universal Video Decoder (UVD). The improvements will allow the new chip(s) to playback video in ultra high definition (UHD) resolutions. Unfortunately, at present there are no commercial UHD movies, hence, a more important feature of future GPUs will be ability to upconvert full-HD Blu-ray movies to higher resolutions.

ATI/AMD did not comment on the news-story.

News Source: http://www.xbitlabs.com/news/video/...Dual_Chip_Flagship_Graphics_Card_Rumours.html

I know they talking efficiency but how much better will 6xxx series Tessellation be? Anyone care to guess. As far as I know, that was the low point the 5xxx series had vs the G100. Also, how would ATI go about making it better than the G100?

 

[rpg.314]

This launch cycle seems to be mirroring the evergreen launch so far.

 

[Mendel]

Having just realized I cannot physically fit 4 large gpus in my P193 case, I was just about to come and ask whether or not there would be a dual gpu 6000 series card and here I already have the answer. Thanks guys

 

[neliz]

Having just realized I cannot physically fit 4 large gpus in my P193 case, I was just about to come and ask whether or not there would be a dual gpu 6000 series card and here I already have the answer. Thanks guys

Most probably yes. If the rumored pin-to-pin compatibility is true, we're looking at a speed bump with architectural tweaks and not an overhaul.

 

[mczak]

Most probably yes. If the rumored pin-to-pin compatibility is true, we're looking at a speed bump with architectural tweaks and not an overhaul.

Why would pin-to-pin compatibility mean it can't be a new architecture? As long as your i/o stays the same I can't really see why you'd need another pin assignment (provided you had enough power pins etc.). Case in point you wouldn't say a Core2 Duo is just "architectural tweaks" of a P4, yet it's pin compatible...

 

[no-X]

I think neliz's point was something like that the pin to pin compatibility eliminates possibility of 384bit memory controller, side-port (or any other alternative way of interconnection) etc.

 

[hkultala]

I think neliz's point was something like that the pin to pin compatibility eliminates possibility of 384bit memory controller, side-port (or any other alternative way of interconnection) etc.

AMD, ATI have not used any non-power-of 2-memory bus widths EVER on any chip, so I consider it quite unlikely they would do it in "R900" either.

And side-port.. that's waste of pins and die size for the >98% of cases where we have only single chip. I'd rather have $250 card that performs well on single card, single chip mode than $280 card that's equally fast on single chip mode but gives slightly better scaling IF paired with another chip/card