AMD: R9xx Speculation

So, what do you think guys? after having a glance at the tidbits of the new architecture, could this be indeed a new R300 as rumoured?.

 

I think the performance of the cards would need to be seen 1st.

 

Indeed, but if AMD hasnt screwed up, its possible to extrapolate rough estimates. I would be mighty surprised if with such stats 6970 wont be faster than GTX580. While 6990 as someone joked would provide "useless" amount of firepower

 

It's not going to be an R300 because GTX580 is already out, and its not NV30.

 

Don't forget even with only one 32bit int mul per clock, the absolute number is still (somewhat) higher than what a GTX580 can do (which has half-rate 32bit int rate). For 32bit int adds that's more than twice as fast as GTX 580 (unless, of course, that's scalar, in which case it'll drop to 1 32bit int add as usual). So that still looks plenty fast to me.

 

And it can't be a new R300 (imho) anyway, since this was such a big leap in all areas - not only performance but also feature wise. Cayman is probably a nice improvement in performance (and it could be a decent improvement in perf/w too which gets more important), but it doesn't really bring anything new to the table feature wise me thinks.

 

That's a mistake. It can do four 32bit integer adds per cycle. An add can be done in each VLIW slot, same as in Cypress (and everything since R600).

Edit:
ISA looks like that (no difference between different generations):

Code:

x: ADD_INT     R0.x,  R1.x,  R2.x
y: ADD_INT     R0.y,  R1.y,  R2.y
z: ADD_INT     R0.z,  R1.z,  R2.z
w: ADD_INT     R0.w,  R1.w,  R2.w

 

Hmm, somehow I'd gotten into my mind that NV is doing fullspeed 32bit INTs

 

That's what they said, tests have shown something else iirc.

 

Well, I hadn't even noticed that one! If it can do 4 FMAs/cycle, there's really no reason it shouldn't be able to do 4 ADDs, anyway.

By the way, does anyone know when the NDA actually expires? I mean the NDA for this presentation, not benchmarks.

 

That's my thinking as well. It appears that the 6950 should be on par (win some/loss some) with the competing current gen card. But that remains to be seen. Another contention is the improved IQ with MLAA along with EQAA and what kind of performance one will get with those cards.

 

Unfortunately the people who know that also couldn't tell us if they wanted to, NDAs are tricky that way.

 

Future proofing doesn't exist. GF 1x0 may be fast with tessellation but in upcoming games another part of the hardware may be bottleknecked in thos egames resulting in the game performing as badly as the cypress platform might. Or cypress leading in other areas of performance might pull away.

Anyway there is a thread on tessellation

 

Oh you're right. The whitepaper said only DP can't be dual issued but two int instructions can. Either that's just not true or it could be artificially limited for consumer parts?

 

Are those different?

 

How and why would they make such a mistake?
They use the Mantissa part of the FP unit only can do 24bit INT unless they have 48bit FP capability.

 

And in many cases for the entire kernel, only half rate 32 bits add is unacceptable, fortunally it's not the case.

32 bit mul at quarter rate is ok but not good, at half rate would be good, since the hardware is capable of 52 bits multiplies at quarter rate couldn't it be a little modified to allow 32 bit mul at half?

 

With FMA the need 48 bit adders for correct results.

Anyway, 32 bits adders are way to cheap to not include...

 

Actually, Fermi has full rate 32-bit int add operations. I just wrote a CUDA kernel to test it out on my GTX 480, and got 644 Giga integer adds/second. The full-rate peak would be 1.4 GHz * 480 SMs= 672 Giga integer adds/second.

Trying the same kernel out with 32-bit int mul operations gave 331 Giga integer muls/second, which does appear to be half rate.

 

Ahh, but still why would ATI be quoting 24bit only?

Perhaps for a few but when you have 1920 of them?