AMD: R9xx Speculation

[Gipsel]

255mm^2, 1.7Bil Transistors, still 1 Tri/Clock, Tessellation improvements coming from thread management and buffering, ~1.5x-2x speed until ~20 Tesselation factor where it tends back to 1x.

oh and 4D!

Yes, just some larger buffers. It's the cheap version but it will suffice in my opinion. Anything more solid for the SIMD layout?

 

[Tchock]

(Up there, one of the slides. 2 HTDP still, probably improved bandwidth and all)

 

[Kaotik]

Slides are out:
http://www.chiphell.com/thread-130729-1-1.html (Login needed)

Key stuff?
MLAA through DirectCompute (DX9-10-11), 255mm^2, 1.7Bil Transistors, still 1 Tri/Clock, Tessellation improvements coming from thread management and buffering, ~1.5x-2x speed until ~20 Tesselation factor where it tends back to 1x.

oh and 4D!

Rehosted by me, can't see 4D? 1120 / 14 = 80, can be 20x4D or 16x(4+1D)

 

[Kaotik]

The rest as I can't put all images in same post

 

[fellix]

So, no parallel setup yet. Looks like this will be saved for Cayman.

 

[Gipsel]

can't see 4D? 1120 / 14 = 80, can be 20x4D or 16x(4+1D)

From the diagram it looks like the normal 4 groups of 4 VLIW units per SIMD engine together with 4 TMUs. So it is effectively the Evergreen layout. No 4 slot VLIW.

 

[AnarchX]

So, no parallel setup yet. Looks like this will be saved for Cayman.

Compare with this:

The dispatch and needed caches seem more parted on Barts sheme.

 

[fellix]

Anything on texturing and AF quality?

Edit:

NVM, that slide got some hints about it --

 

[AnarchX]

Anything on texturing and AF quality?

http://gathering.tweakers.net/forum/list_message/34874406#34874406

I hope this is no fake. :smile:

 

[Squilliam]

Funny thing is that both Nvidia and AMD said "Tessellation done right"

But look at that density! It looks like a mighty fine chip. Its too bad I have something better otherwise I would want this!

 

[fellix]

About the MLAA thing, I wonder if would be possible to be used in conjunction with MSAA -- the last would provide some minimum level of sub-pixel coverage.

 

[rpg.314]

No mention of caches. May be that got pushed to Cayman too.

 

[fellix]

Transistor density is marginally improved in Barts, compared to Cypress. Nothing to write home about.

 

[ZerazaX]

The dispatch and needed caches seem more parted on Barts sheme.

Saw that as well. The difference is probably the most notable part of that diagram, since the rest of it seems copied exactly (sans the 18 SIMDs -> 14)

 

[DarthShader]

The same Watts for almost the same performance?

I do like their approach to tesselation though.

 

[Alexko]

The same Watts for almost the same performance?

I do like their approach to tesselation though.

Getting superior perf/W out of a dense, 900MHz part is quite impressive if you ask me.

Also, it's nice to see that Barts retains 6 display controllers, for full Eyefinity.

 

[GZ007]

The same Watts for almost the same performance?

What else did u expect from the same 40nm process

 

[hkultala]

Saw that as well. The difference is probably the most notable part of that diagram, since the rest of it seems copied exactly (sans the 18 SIMDs -> 14)

Can current radeons execute different shader programs in different SIMD processors?

(Fermi can, but G80-GT200 series can't)?

Could this change be related to that, so that now there are really two "more independent" groups of shaders which can execute 2 different shaders programs, and previously all had to execute same?

 

[DarthShader]

What else did u expect from the same 40nm process

At least 1W lower consumption.

It's the high clock which draws consumption up, compared to 5850. Declaring TDP as 151W sounds almost like an intentional excuse to put the second 6-pin power connector in. I am curious to see how much overclocking headroom there is in those cards.

 

[fellix]

Could this change be related to that, so that now there are really two "more independent" groups of shaders which can execute 2 different shaders programs, and previously all had to execute same?

Dual thread dispatchers are more about better utilization efficiency, me thinks. Parallel/multiple kernel processing is something else, if this is what you mean.