AMD: R9xx Speculation

This is all going to be about the price point I think, well that is what I think the reviewers will ponder about mostly, bang per buck, because they can't go on about the bang in itself as it seems same to last generation.

I would guess AMD wish they could have brought out the faster chip first and then fill in the midrange, alas it seems not to be due to the manufacturer.
 
It's on the 14th.

Actually.. it was already :D.. just depends on what your relationship is with AMD.

Now, I know that even neliz (whom I respect even more than Charlie) hinted at something like "GTX 470 performance @ 1/3 of the die size" a few pages earlier in this thread - but that just
(a) seems too good to be true and
(b) would really make me wonder how <200mm² could honestly be marketed as the new "sweet spot"?
(c) how many AMD engineers sold their solds to the perf/mm² devil to actually achieve (at least) HD 5850 performance @ just 60% of Cypress' die size?

The 1/3rd was a rough number but I was led to believe that the die size was with rumors of old, the cards will definitely be smaller than Cypress cards and with better perf/mm².
 
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The 1/3rd was a rough number but I was led to believe that the die size was with rumors of old, the cards will definitely be smaller than Cypress cards and with better perf/mm².
Thanks for clearing that up.

"Smaller than Cypress" and "better perf/mm²" is to be expected - I just don't believe in Charlie's <200mm² number.

His ~380-400mm² guess for Cayman would also suggest that, within his own logic, the relation between Cayman and Barts would pretty much have to equal the relation between Cypress and Juniper (i.e. "cut in half" in every possible respect). So Cayman @512bit mem interface, 128TMUs, 64 ROPs etc.? No - I think it's more probable that Charlie got something wrong there ...
 
512 bit would make a might Fine 9 part! :D
Thinking about it, if Barts really had 32ROPs@900Mhz, Cayman@32ROPs would actually seem kind of bottlenecked in that regard ... and wanting to add more ROPs would indeed be difficult on a 256bit interface ... :oops:

I have to admit I'm kind of confused now - and I might start to reconsider some things I said.
 
Thinking about it, if Barts really had 32ROPs@900Mhz, Cayman@32ROPs would actually seem kind of bottlenecked in that regard ... and wanting to add more ROPs would indeed be difficult on a 256bit interface ... :oops:

At Northern Island they might decoupled MCs and ROPs with a crossbar, so that ROPs could be per RPE.

Barts: 2 RPEs (24 TMUs, 480SPs, 16 ROPs each) 256-Bit @ ~4Gbps
Cayman: 3 RPEs (32 TMUs, 640SPs, 16 ROPs each) 256-Bit @ ~6Gbps
 
512-bit sounds way overkill for Cayman, doesn't it? I mean, Cypress was fine with its 256-bit bus and 4.8GT/s memory. Cayman can most likely rely on 6~7GT/s, so… maybe 384-bit, but 512?
 
Is anyone else predicting that a x9xx single GPU card will be a somewhat one off event?

Think about it, they're only doing it now because the 32nm shrink was pushed back and became 28nm. For the 7000 series, they can return to somewhat of a sweetspot with an 78xx part and still have it outperform 69xx single GPU parts. So, essentially we get a more power hungry and expensive super high end part now with Cayman, while in 8-12 months we get something only marginally faster (15-25%) but much cheaper to produce and less power hungry - thus fitting back into the sweet spot and being labelled 78xx.

Then we have Barts sucessor, which could have to actually be slower than Barts due to memory bus restraints. If 78xx is in the sweet spot, 77xx may end up too small to have a 256-bit memory bus. Overall I'm predicting a return by the 7 series to what we have with the 5 series. 6 series is just a detour due to a delayed process node.
 
Then we have Barts sucessor, which could have to actually be slower than Barts due to memory bus restraints. If 78xx is in the sweet spot, 77xx may end up too small to have a 256-bit memory bus. Overall I'm predicting a return by the 7 series to what we have with the 5 series. 6 series is just a detour due to a delayed process node.

Dave already explained that the 5 series was actually the detour.
 
512-bit sounds way overkill for Cayman, doesn't it? I mean, Cypress was fine with its 256-bit bus and 4.8GT/s memory. Cayman can most likely rely on 6~7GT/s, so… maybe 384-bit, but 512?
At this point, I honestly don't know what to make of all those different rumors and possible specs anymore, but if Barts indeed has 32ROPs@900Mhz, they probably had to find some way to put more ROPs into Cayman in order to keep the design "balanced" ...

If MCs and ROPs are still connected in the conventional way, it could be something like

Barts = 2x (480SPs, 16ROPs, etc.) @ 256bit
Cayman = 4x (480SPs, 16ROPs, etc.) @ 512bit

or

Barts = 2x (640SPs, 16ROPs, etc.) @ 256bit
Cayman = 3x (640SPs, 16ROPs, etc.) @ 384bit

But really, who knows.
 
Why should Cayman does not have RPEs with more ALUs than Barts?
Cayman is also targeted on HPC market, where it does not need the stuff to make 3D graphics fast, he needs there pure crunching power.

I would not wonder if Cayman XT is ~50% faster in 3D than Barts XT, even the first one has the double number of SPs. These 50% are also there difference between todays HD 5870 and HD 5970
 
Dave already explained that the 5 series was actually the detour.

The 3870, 4870 and 5870 all represented flagship single chip products. Barts would change that pattern. In terms of being a sweet spot play, the 4870 is the only one that qualifies so far IMO. 6870 would be the second.
 
Actually.. it was already :D.. just depends on what your relationship is with AMD...


:LOL: OMG! It's so funny. The guys at AMD are :mad: ... They are not launching a new top secret military weapon but just one ordinary consumer videocard. I cannot believe this is happening. :devilish:
I think they are gathering more and more negative (red) points...
 
Neliz hints at Hardware Morphological Anti-Aliasing on tweakers.net.

Thoughts?
I don't see how a dedicated HW would be justified for such a "loose" AA method, that is no more different than the tons of other post-process image effects. The edge-detect CFAA doesn't have it, why should MLAA?

It could be probably another optimized kernel AA filter, in addition to the already available collection of CFAA modes.
 
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