Jawed
Legend
I reckon the factors in making RV770 pad-limited (any other ideas?):
- power - don't feel like working out how many I/O pads there are, but the remainder should be power related
- complexity of GDDR5 - requires more pads than GDDR4 (RV670 is 192mm² 256-bit GDDR4)
- GDDR5 clocks - presumably higher clocks require more area
- sideport - this is a funny one. It takes something like 5.6mm of perimeter. But there is no need for it to take so much perimeter, as it should be stackable (see how PCI Express is stacked on GT215 - 2 lines of pads along the perimeter instead of a single line). Note also that it's theoretically PCI Express, electrically, but at much lower power. The area consumed by the sideport I/O in RV770 is about 38% of the PCI Express I/O. Which implies to me that stacking should be easier
Against all that is the under bump routing layer patent application. The gist of that is the ability to deliver power to parts of the chip without being limited by the density of solder balls. This should mean it's possible to deliver power to the I/O areas of the chip without cluttering the I/O solder balls with power balls.
http://v3.espacenet.com/publication...T=D&date=20090205&CC=US&NR=2009032941A1&KC=A1
I presume this reduces the "pad limitation" of high bandwidth GDDR5. Having said that, it looks old enough that it should have been part of RV770.
Alternatively this is not about pad limitation, but merely changing the distribution of power solder balls across the surface of the chip (since solder balls are current limited in aggregate). So the solder ball count would remain unchanged, and there'd be no effect on overall pad limit. I don't know how much give and take there is, e.g. some solder balls might have spare current capability before the application of this document's technique.
I wouldn't be surprised if Barts looks the same size as RV770 on the back of its board.
Is that Googlenglish or a proper translation?
