AMD: R7xx Speculation

[Unknown Soldier]

R700 is 55 nanometre

We got confirmation that the R700, a chip that is scheduled for the 1H of 2008, is going to be manufactured at 55 nanometre. The 55 nanometre process is an optical shrink of the 65 nanometre process and it is the logical step for the graphics guys. The CPU guys will go from 65 to 45 nanometre instantly, but the CPU guys didn't use 80 nanometre either as they decided to go from 90 to 65 nanometre.

Our knowledgeable sources also confirmed that R700 is a multi core design and DAAMIT calls it Multi Core Unified Architecture. This sounds like a couple of cores stitched together in a high end chip and a single core for a small chip.

On some previous roadmaps the R700 was scheduled for Q1 2008, but the way ATI has been delaying its products, I think its safer to say first half of 2008. This is what AMD uses for years, so the little ATI will have to fit in.

If the R700 can go up against the G100 remain to be seen.

http://www.fudzilla.com/index.php?option=com_content&task=view&id=1028&Itemid=1

 

[Geeforcer]

Seems kind of early for 55nm.

 

[akira888]

The CPU guys will go from 65 to 45 nanometre instantly, but the CPU guys didn't use 80 nanometre either as they decided to go from 90 to 65 nanometre.

No Fudo, CPU vendors just don't publically announce half-node lithographic shrinks on their products. In fact, video ASIC sellers are virtually alone in the industry in doing so.

 

[silent_guy]

No Fudo, CPU vendors just don't publicly announce half-node lithographic shrinks on their products.

So you're suggesting that they are using half nodes?
CPU vendor aren't exactly shy about exposing gory details about characteristics and technologies used. Meanwhile, for all these years, they kept their half-nodes secret?

In fact, video ASIC sellers are virtually alone in the industry in doing so.

RAM and FPGA companies are very open about processes used. For others, it's not exactly a secret either, it just that consumers don't really give a damn about what's powering their cell phone or washing machine.

Seems kind of early for 55nm.

According to this, it seems to be more or less ready now. Q1 should be no problem (and we all know it'll be Q2 or Q3 anyway, right? )

 

[Star_Hunter]

Hopefully the 55nm won't have the leakage that 80nm had. However, I don't know if you can say that R700 for sure going to be 55nm. R700 should have been in development for a while by now and they likely started targeting 65nm when they started. While I am sure they were aware of 55nm coming down the pipeline, switching from 65nm to 55nm in the middle of development while a good move if they could pull it off, might not happen since they don't want to face more possible delays as they have had enough recently(R520,R600).

 

[Techno+]

Hopefully the 55nm won't have the leakage that 80nm had. However, I don't know if you can say that R700 for sure going to be 55nm. R700 should have been in development for a while by now and they likely started targeting 65nm when they started. While I am sure they were aware of 55nm coming down the pipeline, switching from 65nm to 55nm in the middle of development while a good move if they could pull it off, might not happen since they don't want to face more possible delays as they have had enough recently(R520,R600).

the porting of r600 and r520 took time because they were large chips, if the rumuors are true, R700 is a cluster of samll GPUs. All what ATI needs to do is port this small chip, copy paste and then design the interconnects. This isn't that easy but I'm just trying to say why porting r700 to a new process tech isnt going to take a long time.

 

[Jawed]

ATI has had a long run of bad luck (is it just bad luck?) with half nodes: X700XT on 110nm, RV560/570 on 80nm and R600 on 80nm

The thing that puzzles me about the multi-chip rumour is connecting the damn things. If R600's ring stops are interconnected by a 1024-bit link, is that going to work when the GPU consists of multiple dies, each acting as one ring stop?

Jawed

 

[Techno+]

ATI has had a long run of bad luck (is it just bad luck?) with half nodes: X700XT on 110nm, RV560/570 on 80nm and R600 on 80nm

The thing that puzzles me about the multi-chip rumour is connecting the damn things. If R600's ring stops are interconnected by a 1024-bit link, is that going to work when the GPU consists of multiple dies, each acting as one ring stop?

Jawed

I think the GPUs will use hypertransport 3. AMD has this tech and ATI can use it.

 

[Geo]

They're already at 65nm on some chips.

If R700 is 1H 2008 (i.e. a year from now), and it is 55nm, then I wouldn't be surprised if it wasn't their first chip on 55nm. It was less than a year going 90nm-->80nm for mid/low chips.

 

[Maintank]

Should learn from their mistakes imo and not push a high end device on a new process. Nvidia learned this with the NV30. Now you see low end devices debuted on the new process while their flagship stuff gets out the door with a refresh on a then proven process.

I am "guessing" since the release of this chip is within 9-12 months of the R600, it is a variant of it? Like the R300-R420 or NV40-G70?

 

[Love_In_Rio]

And what would it be ? let´s say 4 chips of about 300 millions of transistors and 300 gflops each ?

 

[Techno+]

And what would it be ? let´s say 4 chips of about 300 millions of transistors and 300 gflops each ?

 

[Sound_Card]

I cant seem to recall, but I thought TSMC's 45nm process was targeted for late summer early fall.

 

[Silent_Buddha]

Well, here's a thought. Jawed seems to think the RV630 might be a well balanced design. And he's posted in other threads where he thinks 4xRV630 might make for a good high end chip.

What would be the possibility of a tweaked RV630 as a base for a multichip design to be used in R700?

After all it's already on 65nm. Total card uses 45w currently. So the chip itself must use quite a bit less than that.

Consider some tweaks to the core and a shrink down to 55nm and then getting multiples to work with each other?

Regards,
SB

 

[Jawed]

Well, here's a thought. Jawed seems to think the RV630 might be a well balanced design.

For a <$150 part yeah.

And he's posted in other threads where he thinks 4xRV630 might make for a good high end chip.

Yeah, I do, but one that comes this year, not in 1 year's time :smile: But as I cautioned, ~1 billion transistors (prolly approaching 500mm2) is just too big for this year ... argh, I dunno.

What would be the possibility of a tweaked RV630 as a base for a multichip design to be used in R700?

I feel kinda stupid for taking the multichip R700 concept seriously. It just sounds mad. It's notable that HD2900XT only has two significant chips on it, the GPU and the Theater chip. This rumoured de-integration is bizarre.

Yet at the same time, 4x RV630 + 33% more ALUs has an intriguing ring to it, per chip:

• 128KB of L2 cache
• 8 TUs
• 160 ALUs
• 1 RBE
• 2 64-bit memory channels
• no AVIVO/UVD

This would require a PCI Express/Framebuffer/AVIVO/UVD/CF chip, much like NVIO.

I just can't see how 4 of these chips can be ring-bussed together. It would require a multi-GHz off-chip bus x2, per chip. 50GB/s per chip-to-chip link in both directions simultaneously. Nuts.

It's worth observing that the link between Xenos and the EDRAM daughter die is 32GB/s, with the two sharing a substrate. The shared substrate, presumably, makes such a connection much easier than if they were mounted on a normal circuit board.

Maybe it's best to think of RV610 (sized-up) repeated 8 times?:

• 64KB of L2 cache
• 4 TUs
• 100 ALUs
• 1 RBE
• 1 64-bit memory channel
• no AVIVO/UVD

It's interesting to note that as the "building block" chip gets smaller, less of its interconnectivity with the world is taken up by a conventional DDR interface (here it's just 64-bits) which leaves more space for 2x 50GB/s of ring-bus connectivity. At the same time, does the chip end up too small? If all the chips are mounted on a common (expensive) substrate (rather than having individual substrates) then maybe the connectivity is feasible?

You could have hours of fun dreaming up GPUs based on this, or a similar, building block. Seems like folly to me, though.

Jawed

 

[Megadrive1988]

I'm thinking R700 is a GPU that will have around 1 billion transistors.

ATI researchers working to develop products with one billion transistors.

http://www.cbc.ca/cp/business/061013/b101328.html
http://tinyurl.com/yvbefk

Unless they were referring to the R800, which Orton mentioned 3 years ago in his B3D interview. however I think R800 will go well beyond 1B tran.

 

[dnavas]

I'm sure I missed it, but, if someone could list the exclusive advantages of multi-chip solutions, I'd sure like to see them.

SLI and Crossfire seem to be the current offerings. I'm sure they make some happy, but from a scalability and programmability point of view, they don't seem ready for primetime....

 

[zealotonous]

I just don't see ATI releasing a brand new architecture 9 months from R600. Since NV30 is often used as a comparison, how long was NV30's lifetime until NV40 was released? Guess I could look that up. If there is going to be a release in Q1 or even H1 of next year, it won't be a major architectural change unless ATI has had a second development team working on this for quite some time. Especially if it is the smaller, multi core architecture that everyone assumes is going to be R700.

 

[Megadrive1988]

I don't expect R700 to be a totally new architecture from R600. I'm thinking R700 will be somewhat like what R420 was to R300.

the next major architecture is probably R800.

 

[AnarchX]

I'm thinking R700 is a GPU that will have around 1 billion transistors.



http://www.cbc.ca/cp/business/061013/b101328.html
http://tinyurl.com/yvbefk

Unless they were referring to the R800, which Orton mentioned 3 years ago in his B3D interview. however I think R800 will go well beyond 1B tran.

But they did not say "on one chip"?

In this interview Peter Edinger from ATi Europe says that we will see multi-core/chip-gpus in the generation after the next . This interview was in 2006.
http://www.golem.de/showhigh2.php?file=/0608/47044.html&wort

And this article from Fuad is based on AMD/ATi document.