AMD: Pirate Islands (R* 3** series) Speculation/Rumor Thread

Nope they are fine with it, which is fun! Great guys

 

Now we need to see the image of aircooled version which will be guarded much stronger. AMD will want to promote fancy-er card first.

 

So what do this litte switch on the side on the end ? dual bios ?

 

VZ and WCC have done their own calculations, far different result.. this said i have absolutely not check their methods .

http://wccftech.com/amd-fiji-die-reconstructed-hbms-huge-gpu-uncovered/

http://videocardz.com/55561/editorial-how-big-is-fiji

 

Oxide has some new toys too.

Graham Sellers ‏@grahamsellers 13h13 hours ago
@dankbaker @repi @AMDRadeon Oh that. That disables the HCF instruction.
https://twitter.com/dankbaker/status/601803058289496064

HCF = Halt and catch fire.

 

I will have said Halt control fan.. switch fan profile of the h2o to full speed.. but im a sad panda, dont have the gpu now.

 

It is just Cape Verde with DDR5. GCN 1.0, released back in 2012 ...

 

Probably doesn't translate well. Graham was just making a joke.
Halt and catch fire

Edit- I'm pretty sure it is a dual bios switch, it is in roughly the same spot as the switch on Hawaii cards.

 

ok lol. Its too early, my brain is not awake for jokes before my first cofee.

 

Turns out that was a typo, it now says

• Native Mini DisplayPort output
• DVI, VGA, dual-link DVI, and HDMI output supported using Mini DisplayPort adapters (sold separately)
• Support for up to 5120-by-2880 resolution at 60Hz on a single external display (model with AMD Radeon R9 M370X only)

 

So it looks like there's an awful lot of wasted interposer space. It really makes you wonder why AMD didn't put all four stacks on the same side, at the expensive of some extra height.

 

If UMC can make interposers larger than 32 x 26mm, then those Fiji die sizes are possible.

WCCF has taken VC's work as far as I can tell and tried to be more accurate. He failed at the first hurdle, stating that the HBM chip is 5mm wide. It's 5.5mm wide. That's a 9% error. That's enough for 2mm of error in the width. He states 21-23mm and I think it's 20mm.

As for the height, I haven't seen most of the source images that VC used so I don't have numbers derived from them. If we take the 26-28mm estimate and adjust for the 9% error, we get 24.5mm.

20 x 24.5 = 491mm².

And all of these numbers (mine, included, from earlier posts) ignore packaging related dimensions. The GPU die is smaller.

 

You need the tracing for the PHY and TSV .. i imagine you have one on a side and the other who come on the other side of the memory package chip, hence why this configuration. Due to the nature of the interposer, i imagine you have too a bit of redundancy on thoses tracing inside the interposer.

it seems all tracing are at the same level, tomorrow, i can imagine the interposer could be made with multiple layers for the tracing.

Seriously, im amazed by all the engineer work and things who have need to be solved for get HBM... so i somewhat trust the work who have been made. The interposer, the TSV's, etc.. On this aspect, i like a lot the Anand article who take everything point by point.

 

Also moving the data from one side of the chip to the other, that is closest to the HBM stacks, wastes additional power.
Locality, locality, locality. If you need to move something you want to move it the least possible distance.

 

LOL! Hella oldskool computing humor!

 

AMD rounded down the hbm size in the slides compared to those from hinyx, so all calc are wrong

 

That was pretty interesting. I dare say it's hard to argue with it, since distinct topologies clearly favour a variety of workloads and peer-types. As a way to cut back on metal layers in the logic die it seems pretty much perfect, if you are going to use an interposer anyway. So really it boils down to the costs and limitations of interposers.

They talk about a 36 x 24mm interposer, which is radically larger than we've been discussing. That increase in width could put Fiji well over 500mm².

In the PDF from Xilinx I linked earlier, there's talk of a technology call SLIT (Silicon-less Interconnect Technology). This is potentially a large saving on interposer costs, because it has no TSVs.

http://electroiq.com/insights-from-...-215-stats-acquisition-will-slit-replace-tsv/

 

Effectively i will not base any calculation, on draw, 3D render or schema who could be really far of the reality.

 

I'm sorry, you're absolutely right. I saw the 9% error and didn't even stop to think about the sign

Yes, those are the dimensions I have been using.

My problem with both sites' numbers is that they've both ignored the possible size of an interposer.

But since I wrote my criticism of their numbers in post 1092, I've realised two things:

1. AMD itself seems to be under the impression that an interposer can be 36 x 24mm. Simply by allowing 12mm for the gaps around the HBM, the GPU can be 24mm wide. Hence my comment in post 1097 that the GPU could be over 500mm². I had used 32mm as the maximum width earlier, which is why I suggested it could be 20mm wide.
   
2. I ignored the possibility that the spacing of the HBMs along each edge are asymmetric, therefore my height estimate was too low. The collage even shows this, but I ignored it.

If you take the maximum size of the interposer as being 36 x 24mm, then I think the maximum GPU die size is 24 x 23mm = 552mm². Based on the pictures I think the height is less than 23mm, because the spare interposer area at the top edge seems to be more than 0.5mm.